jay@aura-R528 syn$ make distclean
rm -rf *.ngc *.ncd *.ngd *.bit
make clean
make[1]: Entering directory `/home/aurabindo/minsoc/syn'
rm -rf _xmsgs xst xlnx_auto_0_xdb
rm -rf *.xst *.xrpt *.srp *.lso *.log *.bld *.lst *.twr *.ise *.map *.mrp *.ngm *.pcf *.psr *.xml *.pad *.par *.ptwx *.bgn *.unroutes *.xpi minsoc_par_pad* *.xwbt *.html
make[1]: Leaving directory `/home/aurabindo/minsoc/syn'
jay@aura-R528 syn$ make or1200
make prepare
make[1]: Entering directory `/home/aurabindo/minsoc/syn'
rm -rf xst
mkdir xst
make[1]: Leaving directory `/home/aurabindo/minsoc/syn'
xst -ifn "..//syn/buildSupport/or1200_top.xst"
Release 13.2 - xst O.61xd (lin)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
-->
Parameter TMPDIR set to ./xst


Total REAL time to Xst completion: 2.00 secs
Total CPU time to Xst completion: 0.14 secs

-->

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
	9.1) Device utilization summary
	9.2) Partition Resource Summary
	9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Verilog Include Directory          : { "/home/aurabindo/minsoc/prj/../rtl/verilog/or1200/rtl/verilog" }
Input File Name                    : "/home/aurabindo/minsoc/prj/../prj/xilinx/or1200_top.prj"
Input Format                       : Verilog

---- Target Parameters
Output File Name                   : "or1200_top"
Output Format                      : NGC
Target Device                      : xc3s500e-4-fg320

---- Source Options
Top Module Name                    : or1200_top

---- Target Options
Add IO Buffers                     : no

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "/home/aurabindo/minsoc/prj/../prj/xilinx/or1200_top.prj" in library work
ERROR:HDLParsers:3464 - Library work mapped to physical location xst/work does not exist.
ERROR:HDLCompilers:219 - Open of logical library 'work' failed
Analysis of file <"/home/aurabindo/minsoc/prj/../prj/xilinx/or1200_top.prj"> failed.
-->


Total memory usage is 147460 kilobytes

Number of errors   :    2 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)

make: *** [or1200_top.ngc] Error 6