CU

-------------------------------------------------------------------------
-- Design unit:
-- Description:
-------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.R8_pkg.all;

entity uC_R8 is
    port (
        clk     : in std_logic;
        rst     : in std_logic;
        port_a  : inout std_logic_vector(15 downto 0);
        port_b  : inout std_logic_vector(15 downto 0)
    );
end uC_R8;

architecture structural of uC_R8 is

    signal clk_aux, rst_aux :  std_logic;
    signal rw, ce, ce_n, we_n, oe_n, ce_ports, ce_memo : std_logic;
    signal dataR8, dataBus, addressR8, address : std_logic_vector(15 downto 0);

begin

        MICROCONTROLADOR: entity work.R8
        port map (
            clk         => clk_aux,
            rst         => rst_aux,
            data_in     => dataBus,
            data_out    => dataR8,
            address     => addressR8,
            ce          => ce,
            rw          => rw
        );

        RAM : entity work.Memory
        generic map (
           SIZE         => 1024,    -- 1024 words (2KB)
           imageFileName => "teste1.txt"--"../sim/Todas_Instrucoes_R8.txt"
        )
        port map (
            clk     => clk_aux,
            ce_n    => ce_memo,
            we_n    => we_n,
            oe_n    => oe_n,
            data    => dataBus,
            address => addressR8
        );


        BIDIRECTIONAL_PORT_A: entity work.BidirectionalPort
        generic map(
            DATA_DIRECTION_ADDR => x"FFF0",
            OUTPUT_DATA_ADDR    => x"FFF1",
            INPUT_DATA_ADDR     => x"FFF2"
        )
        port map (
            clk         => clk_aux,
            rst         => rst_aux,
            address     => addressR8,
            data        => dataBus,
            port_io     => port_a,
            ce          => ce_ports,
            rw          => rw
        );

        BIDIRECTIONAL_PORT_B: entity work.BidirectionalPort
        generic map(
            DATA_DIRECTION_ADDR => x"FFF3",
            OUTPUT_DATA_ADDR    => x"FFF4",
            INPUT_DATA_ADDR     => x"FFF5"
        )
        port map (
            clk         => clk_aux,
            rst         => rst_aux,
            address     => addressR8,
            data        => dataBus,
            port_io     => port_b,
            ce          => ce_ports,
            rw          => rw
        );


    -- Memory access control signals
    ce_n <= '0' when (ce='1') else '1';
    oe_n <= '0' when (ce='1' and rw='1') else '1';
    we_n <= '0' when (ce='1' and rw='0') else '1';

    ce_ports <= ce when addressR8 > x"FFEF" else '0';
    ce_memo <= ce_n when addressR8 < x"FFF0" else '0';

    dataBus <= dataR8 when ce = '1' and rw='0' else     -- Writing access
            (others => 'Z');
    clk_aux <= clk;
    rst_aux <= rst;
end structural;