LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY hello_world IS
    GENERIC (
        counterBitNb : POSITIVE := 18;
        mode : INTEGER RANGE (0 TO 1) := 0
    );
    PORT (
        clk        : IN std_logic;
        switch     : IN std_logic;
        led        : OUT std_logic;
        led1       : OUT std_logic;
        input      : IN std_ulogic;
        debounced  : OUT std_ulogic;
        reset      : IN std_ulogic
    );
END hello_world;
ARCHITECTURE rtl OF hello_world IS
    SIGNAL cnt : unsigned(24 DOWNTO 0);
    SIGNAL cnt : unsigned(counterBitNb - 1 DOWNTO 0);
    SIGNAL debounced_m0 : std_ulogic;
    SIGNAL debounced_m1 : std_ulogic;
BEGIN
    counter : PROCESS(reset, clock)
    BEGIN
        IF reset = '1' THEN
            cnt <= (OTHERS => '0');
        ELSIF rising_edge(clock) THEN
            IF mode = 0 THEN
                IF input = '1' THEN
                    cnt <= (OTHERS => '1');
                ELSE
                    IF cnt /= 0 THEN
                        cnt <= cnt - 1;
                    END IF;
                END IF;
            ELSE
                IF input = '0' THEN
                    cnt <= (OTHERS => '1');
                ELSE
                    IF cnt /= 0 THEN
                        cnt <= cnt - 1;
                    END IF;
                END IF;
            END IF;
        END IF;
    END PROCESS counter;
    debounced_m0 <= '1' WHEN cnt /= 0
                    ELSE '0';
    debounced_m1 <= '1' WHEN cnt = 0
                    ELSE '0';
    debounced <= debounced_m0 WHEN mode = 0
                 ELSE debounced_m1;
    cnt <= cnt + 1 WHEN rising_edge(clk);
    led <= cnt(22);
    led1 <= debounced;
    switch <= input;
END rtl;