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  1. iming constraint: TS_clk_125_tx_clkout0 = PERIOD TIMEGRP "clk_125_tx_clkout0" TS_clock * 1.25 HIGH 50%;
  2. For more information, see Period Analysis in the Timing Closure User Guide (UG612).
  3. 1220637 paths analyzed, 86118 endpoints analyzed, 15777 failing endpoints
  4. 15777 timing errors detected. (15777 setup errors, 0 hold errors, 0 component switching limit errors)
  5. Minimum period is 16.913ns.
  6. --------------------------------------------------------------------------------
  7.  
  8. Paths for end point packet_sender/send_buffer_10009 (SLICE_X30Y116.D2), 70 paths
  9. --------------------------------------------------------------------------------
  10. Slack (setup path): -8.913ns (requirement - (data path - clock path skew + uncertainty))
  11. Source: packet_sender/pixel_cnt_2 (FF)
  12. Destination: packet_sender/send_buffer_10009 (FF)
  13. Requirement: 8.000ns
  14. Data Path Delay: 16.760ns (Levels of Logic = 4)
  15. Clock Path Skew: -0.044ns (0.470 - 0.514)
  16. Source Clock: clk_125 rising at 0.000ns
  17. Destination Clock: clk_125 rising at 8.000ns
  18. Clock Uncertainty: 0.109ns
  19.  
  20. Clock Uncertainty: 0.109ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
  21. Total System Jitter (TSJ): 0.070ns
  22. Discrete Jitter (DJ): 0.205ns
  23. Phase Error (PE): 0.000ns
  24.  
  25. Maximum Data Path at Slow Process Corner: packet_sender/pixel_cnt_2 to packet_sender/send_buffer_10009
  26. Location Delay type Delay(ns) Physical Resource
  27. Logical Resource(s)
  28. ------------------------------------------------- -------------------
  29. SLICE_X34Y64.AQ Tcko 0.447 packet_sender/pixel_cnt<2>
  30. packet_sender/pixel_cnt_2
  31. SLICE_X25Y64.D4 net (fanout=9) 1.598 packet_sender/pixel_cnt<2>
  32. SLICE_X25Y64.D Tilo 0.259 simple_gemac_wrapper/tx_2clk_fifo/shortfifo/full_1
  33. packet_sender/GND_53_o_GND_53_o_equal_47_o<15>_SW1
  34. SLICE_X31Y58.C1 net (fanout=6) 1.912 N9586
  35. SLICE_X31Y58.C Tilo 0.259 packet_sender/data_15
  36. packet_sender/en_fifo_full_AND_176_o1_5
  37. SLICE_X33Y46.A5 net (fanout=4) 2.177 packet_sender/en_fifo_full_AND_176_o1_1
  38. SLICE_X33Y46.A Tilo 0.259 packet_sender/send_buffer<7259>
  39. packet_sender/nxt_send_buffer<1008>21_8
  40. SLICE_X30Y116.D2 net (fanout=1035) 9.560 packet_sender/nxt_send_buffer<1008>217
  41. SLICE_X30Y116.CLK Tas 0.289 packet_sender/send_buffer<10009>
  42. packet_sender/nxt_send_buffer<10009>
  43. packet_sender/send_buffer_10009
  44. ------------------------------------------------- ---------------------------
  45. Total 16.760ns (1.513ns logic, 15.247ns route)
  46. (9.0% logic, 91.0% route)
  47.  
  48. --------------------------------------------------------------------------------
  49. Slack (setup path): -8.821ns (requirement - (data path - clock path skew + uncertainty))
  50. Source: packet_sender/fifo_full (FF)
  51. Destination: packet_sender/send_buffer_10009 (FF)
  52. Requirement: 8.000ns
  53. Data Path Delay: 16.649ns (Levels of Logic = 3)
  54. Clock Path Skew: -0.063ns (0.470 - 0.533)
  55. Source Clock: clk_125 rising at 0.000ns
  56. Destination Clock: clk_125 rising at 8.000ns
  57. Clock Uncertainty: 0.109ns
  58.  
  59. Clock Uncertainty: 0.109ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
  60. Total System Jitter (TSJ): 0.070ns
  61. Discrete Jitter (DJ): 0.205ns
  62. Phase Error (PE): 0.000ns
  63.  
  64. Maximum Data Path at Slow Process Corner: packet_sender/fifo_full to packet_sender/send_buffer_10009
  65. Location Delay type Delay(ns) Physical Resource
  66. Logical Resource(s)
  67. ------------------------------------------------- -------------------
  68. SLICE_X27Y65.AQ Tcko 0.391 packet_sender/fifo_full
  69. packet_sender/fifo_full
  70. SLICE_X49Y45.A3 net (fanout=14) 4.518 packet_sender/fifo_full
  71. SLICE_X49Y45.A Tilo 0.259 packet_sender/nxt_send_buffer<1008>218
  72. packet_sender/en_fifo_full_AND_173_o2_6
  73. SLICE_X33Y46.A4 net (fanout=4) 1.373 packet_sender/en_fifo_full_AND_173_o2_1
  74. SLICE_X33Y46.A Tilo 0.259 packet_sender/send_buffer<7259>
  75. packet_sender/nxt_send_buffer<1008>21_8
  76. SLICE_X30Y116.D2 net (fanout=1035) 9.560 packet_sender/nxt_send_buffer<1008>217
  77. SLICE_X30Y116.CLK Tas 0.289 packet_sender/send_buffer<10009>
  78. packet_sender/nxt_send_buffer<10009>
  79. packet_sender/send_buffer_10009
  80. ------------------------------------------------- ---------------------------
  81. Total 16.649ns (1.198ns logic, 15.451ns route)
  82. (7.2% logic, 92.8% route)
  83.  
  84. --------------------------------------------------------------------------------
  85. Slack (setup path): -8.628ns (requirement - (data path - clock path skew + uncertainty))
  86. Source: packet_sender/pixel_cnt_7 (FF)
  87. Destination: packet_sender/send_buffer_10009 (FF)
  88. Requirement: 8.000ns
  89. Data Path Delay: 16.477ns (Levels of Logic = 3)
  90. Clock Path Skew: -0.042ns (0.470 - 0.512)
  91. Source Clock: clk_125 rising at 0.000ns
  92. Destination Clock: clk_125 rising at 8.000ns
  93. Clock Uncertainty: 0.109ns
  94.  
  95. Clock Uncertainty: 0.109ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
  96. Total System Jitter (TSJ): 0.070ns
  97. Discrete Jitter (DJ): 0.205ns
  98. Phase Error (PE): 0.000ns
  99.  
  100. Maximum Data Path at Slow Process Corner: packet_sender/pixel_cnt_7 to packet_sender/send_buffer_10009
  101. Location Delay type Delay(ns) Physical Resource
  102. Logical Resource(s)
  103. ------------------------------------------------- -------------------
  104. SLICE_X30Y66.AQ Tcko 0.447 packet_sender/pixel_cnt<7>
  105. packet_sender/pixel_cnt_7
  106. SLICE_X49Y45.A2 net (fanout=50) 4.290 packet_sender/pixel_cnt<7>
  107. SLICE_X49Y45.A Tilo 0.259 packet_sender/nxt_send_buffer<1008>218
  108. packet_sender/en_fifo_full_AND_173_o2_6
  109. SLICE_X33Y46.A4 net (fanout=4) 1.373 packet_sender/en_fifo_full_AND_173_o2_1
  110. SLICE_X33Y46.A Tilo 0.259 packet_sender/send_buffer<7259>
  111. packet_sender/nxt_send_buffer<1008>21_8
  112. SLICE_X30Y116.D2 net (fanout=1035) 9.560 packet_sender/nxt_send_buffer<1008>217
  113. SLICE_X30Y116.CLK Tas 0.289 packet_sender/send_buffer<10009>
  114. packet_sender/nxt_send_buffer<10009>
  115. packet_sender/send_buffer_10009
  116. ------------------------------------------------- ---------------------------
  117. Total 16.477ns (1.254ns logic, 15.223ns route)
  118. (7.6% logic, 92.4% route)
  119.  
  120. --------------------------------------------------------------------------------
  121.  
  122. Paths for end point packet_sender/send_buffer_10018 (SLICE_X32Y116.A1), 70 paths
  123. --------------------------------------------------------------------------------
  124. Slack (setup path): -8.747ns (requirement - (data path - clock path skew + uncertainty))
  125. Source: packet_sender/pixel_cnt_2 (FF)
  126. Destination: packet_sender/send_buffer_10018 (FF)
  127. Requirement: 8.000ns
  128. Data Path Delay: 16.595ns (Levels of Logic = 4)
  129. Clock Path Skew: -0.043ns (0.471 - 0.514)
  130. Source Clock: clk_125 rising at 0.000ns
  131. Destination Clock: clk_125 rising at 8.000ns
  132. Clock Uncertainty: 0.109ns
  133.  
  134. Clock Uncertainty: 0.109ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
  135. Total System Jitter (TSJ): 0.070ns
  136. Discrete Jitter (DJ): 0.205ns
  137. Phase Error (PE): 0.000ns
  138.  
  139. Maximum Data Path at Slow Process Corner: packet_sender/pixel_cnt_2 to packet_sender/send_buffer_10018
  140. Location Delay type Delay(ns) Physical Resource
  141. Logical Resource(s)
  142. ------------------------------------------------- -------------------
  143. SLICE_X34Y64.AQ Tcko 0.447 packet_sender/pixel_cnt<2>
  144. packet_sender/pixel_cnt_2
  145. SLICE_X25Y64.D4 net (fanout=9) 1.598 packet_sender/pixel_cnt<2>
  146. SLICE_X25Y64.D Tilo 0.259 simple_gemac_wrapper/tx_2clk_fifo/shortfifo/full_1
  147. packet_sender/GND_53_o_GND_53_o_equal_47_o<15>_SW1
  148. SLICE_X31Y58.C1 net (fanout=6) 1.912 N9586
  149. SLICE_X31Y58.C Tilo 0.259 packet_sender/data_15
  150. packet_sender/en_fifo_full_AND_176_o1_5
  151. SLICE_X33Y46.A5 net (fanout=4) 2.177 packet_sender/en_fifo_full_AND_176_o1_1
  152. SLICE_X33Y46.A Tilo 0.259 packet_sender/send_buffer<7259>
  153. packet_sender/nxt_send_buffer<1008>21_8
  154. SLICE_X32Y116.A1 net (fanout=1035) 9.343 packet_sender/nxt_send_buffer<1008>217
  155. SLICE_X32Y116.CLK Tas 0.341 packet_sender/send_buffer<10020>
  156. packet_sender/nxt_send_buffer<10018>
  157. packet_sender/send_buffer_10018
  158. ------------------------------------------------- ---------------------------
  159. Total 16.595ns (1.565ns logic, 15.030ns route)
  160. (9.4% logic, 90.6% route)
  161.  
  162. --------------------------------------------------------------------------------
  163. Slack (setup path): -8.655ns (requirement - (data path - clock path skew + uncertainty))
  164. Source: packet_sender/fifo_full (FF)
  165. Destination: packet_sender/send_buffer_10018 (FF)
  166. Requirement: 8.000ns
  167. Data Path Delay: 16.484ns (Levels of Logic = 3)
  168. Clock Path Skew: -0.062ns (0.471 - 0.533)
  169. Source Clock: clk_125 rising at 0.000ns
  170. Destination Clock: clk_125 rising at 8.000ns
  171. Clock Uncertainty: 0.109ns
  172.  
  173. Clock Uncertainty: 0.109ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
  174. Total System Jitter (TSJ): 0.070ns
  175. Discrete Jitter (DJ): 0.205ns
  176. Phase Error (PE): 0.000ns
  177.  
  178. Maximum Data Path at Slow Process Corner: packet_sender/fifo_full to packet_sender/send_buffer_10018
  179. Location Delay type Delay(ns) Physical Resource
  180. Logical Resource(s)
  181. ------------------------------------------------- -------------------
  182. SLICE_X27Y65.AQ Tcko 0.391 packet_sender/fifo_full
  183. packet_sender/fifo_full
  184. SLICE_X49Y45.A3 net (fanout=14) 4.518 packet_sender/fifo_full
  185. SLICE_X49Y45.A Tilo 0.259 packet_sender/nxt_send_buffer<1008>218
  186. packet_sender/en_fifo_full_AND_173_o2_6
  187. SLICE_X33Y46.A4 net (fanout=4) 1.373 packet_sender/en_fifo_full_AND_173_o2_1
  188. SLICE_X33Y46.A Tilo 0.259 packet_sender/send_buffer<7259>
  189. packet_sender/nxt_send_buffer<1008>21_8
  190. SLICE_X32Y116.A1 net (fanout=1035) 9.343 packet_sender/nxt_send_buffer<1008>217
  191. SLICE_X32Y116.CLK Tas 0.341 packet_sender/send_buffer<10020>
  192. packet_sender/nxt_send_buffer<10018>
  193. packet_sender/send_buffer_10018
  194. ------------------------------------------------- ---------------------------
  195. Total 16.484ns (1.250ns logic, 15.234ns route)
  196. (7.6% logic, 92.4% route)
  197.  
  198. --------------------------------------------------------------------------------
  199. Slack (setup path): -8.462ns (requirement - (data path - clock path skew + uncertainty))
  200. Source: packet_sender/pixel_cnt_7 (FF)
  201. Destination: packet_sender/send_buffer_10018 (FF)
  202. Requirement: 8.000ns
  203. Data Path Delay: 16.312ns (Levels of Logic = 3)
  204. Clock Path Skew: -0.041ns (0.471 - 0.512)
  205. Source Clock: clk_125 rising at 0.000ns
  206. Destination Clock: clk_125 rising at 8.000ns
  207. Clock Uncertainty: 0.109ns
  208.  
  209. Clock Uncertainty: 0.109ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
  210. Total System Jitter (TSJ): 0.070ns
  211. Discrete Jitter (DJ): 0.205ns
  212. Phase Error (PE): 0.000ns
  213.  
  214. Maximum Data Path at Slow Process Corner: packet_sender/pixel_cnt_7 to packet_sender/send_buffer_10018
  215. Location Delay type Delay(ns) Physical Resource
  216. Logical Resource(s)
  217. ------------------------------------------------- -------------------
  218. SLICE_X30Y66.AQ Tcko 0.447 packet_sender/pixel_cnt<7>
  219. packet_sender/pixel_cnt_7
  220. SLICE_X49Y45.A2 net (fanout=50) 4.290 packet_sender/pixel_cnt<7>
  221. SLICE_X49Y45.A Tilo 0.259 packet_sender/nxt_send_buffer<1008>218
  222. packet_sender/en_fifo_full_AND_173_o2_6
  223. SLICE_X33Y46.A4 net (fanout=4) 1.373 packet_sender/en_fifo_full_AND_173_o2_1
  224. SLICE_X33Y46.A Tilo 0.259 packet_sender/send_buffer<7259>
  225. packet_sender/nxt_send_buffer<1008>21_8
  226. SLICE_X32Y116.A1 net (fanout=1035) 9.343 packet_sender/nxt_send_buffer<1008>217
  227. SLICE_X32Y116.CLK Tas 0.341 packet_sender/send_buffer<10020>
  228. packet_sender/nxt_send_buffer<10018>
  229. packet_sender/send_buffer_10018
  230. ------------------------------------------------- ---------------------------
  231. Total 16.312ns (1.306ns logic, 15.006ns route)
  232. (8.0% logic, 92.0% route)
  233.  
  234. --------------------------------------------------------------------------------
  235.  
  236. Paths for end point packet_sender/send_buffer_10013 (SLICE_X33Y115.D2), 70 paths
  237. --------------------------------------------------------------------------------
  238. Slack (setup path): -8.675ns (requirement - (data path - clock path skew + uncertainty))
  239. Source: packet_sender/pixel_cnt_2 (FF)
  240. Destination: packet_sender/send_buffer_10013 (FF)
  241. Requirement: 8.000ns
  242. Data Path Delay: 16.525ns (Levels of Logic = 4)
  243. Clock Path Skew: -0.041ns (0.473 - 0.514)
  244. Source Clock: clk_125 rising at 0.000ns
  245. Destination Clock: clk_125 rising at 8.000ns
  246. Clock Uncertainty: 0.109ns
  247.  
  248. Clock Uncertainty: 0.109ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
  249. Total System Jitter (TSJ): 0.070ns
  250. Discrete Jitter (DJ): 0.205ns
  251. Phase Error (PE): 0.000ns
  252.  
  253. Maximum Data Path at Slow Process Corner: packet_sender/pixel_cnt_2 to packet_sender/send_buffer_10013
  254. Location Delay type Delay(ns) Physical Resource
  255. Logical Resource(s)
  256. ------------------------------------------------- -------------------
  257. SLICE_X34Y64.AQ Tcko 0.447 packet_sender/pixel_cnt<2>
  258. packet_sender/pixel_cnt_2
  259. SLICE_X25Y64.D4 net (fanout=9) 1.598 packet_sender/pixel_cnt<2>
  260. SLICE_X25Y64.D Tilo 0.259 simple_gemac_wrapper/tx_2clk_fifo/shortfifo/full_1
  261. packet_sender/GND_53_o_GND_53_o_equal_47_o<15>_SW1
  262. SLICE_X31Y58.C1 net (fanout=6) 1.912 N9586
  263. SLICE_X31Y58.C Tilo 0.259 packet_sender/data_15
  264. packet_sender/en_fifo_full_AND_176_o1_5
  265. SLICE_X33Y46.A5 net (fanout=4) 2.177 packet_sender/en_fifo_full_AND_176_o1_1
  266. SLICE_X33Y46.A Tilo 0.259 packet_sender/send_buffer<7259>
  267. packet_sender/nxt_send_buffer<1008>21_8
  268. SLICE_X33Y115.D2 net (fanout=1035) 9.292 packet_sender/nxt_send_buffer<1008>217
  269. SLICE_X33Y115.CLK Tas 0.322 packet_sender/send_buffer<10013>
  270. packet_sender/nxt_send_buffer<10013>
  271. packet_sender/send_buffer_10013
  272. ------------------------------------------------- ---------------------------
  273. Total 16.525ns (1.546ns logic, 14.979ns route)
  274. (9.4% logic, 90.6% route)
  275.  
  276. --------------------------------------------------------------------------------
  277. Slack (setup path): -8.583ns (requirement - (data path - clock path skew + uncertainty))
  278. Source: packet_sender/fifo_full (FF)
  279. Destination: packet_sender/send_buffer_10013 (FF)
  280. Requirement: 8.000ns
  281. Data Path Delay: 16.414ns (Levels of Logic = 3)
  282. Clock Path Skew: -0.060ns (0.473 - 0.533)
  283. Source Clock: clk_125 rising at 0.000ns
  284. Destination Clock: clk_125 rising at 8.000ns
  285. Clock Uncertainty: 0.109ns
  286.  
  287. Clock Uncertainty: 0.109ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
  288. Total System Jitter (TSJ): 0.070ns
  289. Discrete Jitter (DJ): 0.205ns
  290. Phase Error (PE): 0.000ns
  291.  
  292. Maximum Data Path at Slow Process Corner: packet_sender/fifo_full to packet_sender/send_buffer_10013
  293. Location Delay type Delay(ns) Physical Resource
  294. Logical Resource(s)
  295. ------------------------------------------------- -------------------
  296. SLICE_X27Y65.AQ Tcko 0.391 packet_sender/fifo_full
  297. packet_sender/fifo_full
  298. SLICE_X49Y45.A3 net (fanout=14) 4.518 packet_sender/fifo_full
  299. SLICE_X49Y45.A Tilo 0.259 packet_sender/nxt_send_buffer<1008>218
  300. packet_sender/en_fifo_full_AND_173_o2_6
  301. SLICE_X33Y46.A4 net (fanout=4) 1.373 packet_sender/en_fifo_full_AND_173_o2_1
  302. SLICE_X33Y46.A Tilo 0.259 packet_sender/send_buffer<7259>
  303. packet_sender/nxt_send_buffer<1008>21_8
  304. SLICE_X33Y115.D2 net (fanout=1035) 9.292 packet_sender/nxt_send_buffer<1008>217
  305. SLICE_X33Y115.CLK Tas 0.322 packet_sender/send_buffer<10013>
  306. packet_sender/nxt_send_buffer<10013>
  307. packet_sender/send_buffer_10013
  308. ------------------------------------------------- ---------------------------
  309. Total 16.414ns (1.231ns logic, 15.183ns route)
  310. (7.5% logic, 92.5% route)
  311.  
  312. --------------------------------------------------------------------------------
  313. Slack (setup path): -8.390ns (requirement - (data path - clock path skew + uncertainty))
  314. Source: packet_sender/pixel_cnt_7 (FF)
  315. Destination: packet_sender/send_buffer_10013 (FF)
  316. Requirement: 8.000ns
  317. Data Path Delay: 16.242ns (Levels of Logic = 3)
  318. Clock Path Skew: -0.039ns (0.473 - 0.512)
  319. Source Clock: clk_125 rising at 0.000ns
  320. Destination Clock: clk_125 rising at 8.000ns
  321. Clock Uncertainty: 0.109ns
  322.  
  323. Clock Uncertainty: 0.109ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
  324. Total System Jitter (TSJ): 0.070ns
  325. Discrete Jitter (DJ): 0.205ns
  326. Phase Error (PE): 0.000ns
  327.  
  328. Maximum Data Path at Slow Process Corner: packet_sender/pixel_cnt_7 to packet_sender/send_buffer_10013
  329. Location Delay type Delay(ns) Physical Resource
  330. Logical Resource(s)
  331. ------------------------------------------------- -------------------
  332. SLICE_X30Y66.AQ Tcko 0.447 packet_sender/pixel_cnt<7>
  333. packet_sender/pixel_cnt_7
  334. SLICE_X49Y45.A2 net (fanout=50) 4.290 packet_sender/pixel_cnt<7>
  335. SLICE_X49Y45.A Tilo 0.259 packet_sender/nxt_send_buffer<1008>218
  336. packet_sender/en_fifo_full_AND_173_o2_6
  337. SLICE_X33Y46.A4 net (fanout=4) 1.373 packet_sender/en_fifo_full_AND_173_o2_1
  338. SLICE_X33Y46.A Tilo 0.259 packet_sender/send_buffer<7259>
  339. packet_sender/nxt_send_buffer<1008>21_8
  340. SLICE_X33Y115.D2 net (fanout=1035) 9.292 packet_sender/nxt_send_buffer<1008>217
  341. SLICE_X33Y115.CLK Tas 0.322 packet_sender/send_buffer<10013>
  342. packet_sender/nxt_send_buffer<10013>
  343. packet_sender/send_buffer_10013
  344. ------------------------------------------------- ---------------------------
  345. Total 16.242ns (1.287ns logic, 14.955ns route)
  346. (7.9% logic, 92.1% route)
  347.  
  348. --------------------------------------------------------------------------------
  349.  
  350. Hold Paths: TS_clk_125_tx_clkout0 = PERIOD TIMEGRP "clk_125_tx_clkout0" TS_clock * 1.25
  351. HIGH 50%;
  352. --------------------------------------------------------------------------------
  353.  
  354. Paths for end point simple_gemac_wrapper/simple_gemac/simple_gemac_tx/pause_time_held_7 (SLICE_X44Y71.CE), 1 path
  355. --------------------------------------------------------------------------------
  356. Slack (hold path): 0.279ns (requirement - (clock path skew + uncertainty - data path))
  357. Source: simple_gemac_wrapper/flow_ctrl_rx/pause_req (FF)
  358. Destination: simple_gemac_wrapper/simple_gemac/simple_gemac_tx/pause_time_held_7 (FF)
  359. Requirement: 0.000ns
  360. Data Path Delay: 0.283ns (Levels of Logic = 0)
  361. Clock Path Skew: 0.004ns (0.065 - 0.061)
  362. Source Clock: clk_125 rising at 8.000ns
  363. Destination Clock: clk_125 rising at 8.000ns
  364. Clock Uncertainty: 0.000ns
  365.  
  366. Minimum Data Path at Fast Process Corner: simple_gemac_wrapper/flow_ctrl_rx/pause_req to simple_gemac_wrapper/simple_gemac/simple_gemac_tx/pause_time_held_7
  367. Location Delay type Delay(ns) Physical Resource
  368. Logical Resource(s)
  369. ------------------------------------------------- -------------------
  370. SLICE_X44Y72.AQ Tcko 0.234 simple_gemac_wrapper/flow_ctrl_rx/pause_req
  371. simple_gemac_wrapper/flow_ctrl_rx/pause_req
  372. SLICE_X44Y71.CE net (fanout=5) 0.157 simple_gemac_wrapper/flow_ctrl_rx/pause_req
  373. SLICE_X44Y71.CLK Tckce (-Th) 0.108 simple_gemac_wrapper/simple_gemac/simple_gemac_tx/pause_time_held<7>
  374. simple_gemac_wrapper/simple_gemac/simple_gemac_tx/pause_time_held_7
  375. ------------------------------------------------- ---------------------------
  376. Total 0.283ns (0.126ns logic, 0.157ns route)
  377. (44.5% logic, 55.5% route)
  378.  
  379. --------------------------------------------------------------------------------
  380.  
  381. Paths for end point simple_gemac_wrapper/simple_gemac/simple_gemac_tx/pause_time_held_6 (SLICE_X44Y71.CE), 1 path
  382. --------------------------------------------------------------------------------
  383. Slack (hold path): 0.283ns (requirement - (clock path skew + uncertainty - data path))
  384. Source: simple_gemac_wrapper/flow_ctrl_rx/pause_req (FF)
  385. Destination: simple_gemac_wrapper/simple_gemac/simple_gemac_tx/pause_time_held_6 (FF)
  386. Requirement: 0.000ns
  387. Data Path Delay: 0.287ns (Levels of Logic = 0)
  388. Clock Path Skew: 0.004ns (0.065 - 0.061)
  389. Source Clock: clk_125 rising at 8.000ns
  390. Destination Clock: clk_125 rising at 8.000ns
  391. Clock Uncertainty: 0.000ns
  392.  
  393. Minimum Data Path at Fast Process Corner: simple_gemac_wrapper/flow_ctrl_rx/pause_req to simple_gemac_wrapper/simple_gemac/simple_gemac_tx/pause_time_held_6
  394. Location Delay type Delay(ns) Physical Resource
  395. Logical Resource(s)
  396. ------------------------------------------------- -------------------
  397. SLICE_X44Y72.AQ Tcko 0.234 simple_gemac_wrapper/flow_ctrl_rx/pause_req
  398. simple_gemac_wrapper/flow_ctrl_rx/pause_req
  399. SLICE_X44Y71.CE net (fanout=5) 0.157 simple_gemac_wrapper/flow_ctrl_rx/pause_req
  400. SLICE_X44Y71.CLK Tckce (-Th) 0.104 simple_gemac_wrapper/simple_gemac/simple_gemac_tx/pause_time_held<7>
  401. simple_gemac_wrapper/simple_gemac/simple_gemac_tx/pause_time_held_6
  402. ------------------------------------------------- ---------------------------
  403. Total 0.287ns (0.130ns logic, 0.157ns route)
  404. (45.3% logic, 54.7% route)
  405.  
  406. --------------------------------------------------------------------------------
  407.  
  408. Paths for end point simple_gemac_wrapper/simple_gemac/simple_gemac_tx/pause_time_held_5 (SLICE_X44Y71.CE), 1 path
  409. --------------------------------------------------------------------------------
  410. Slack (hold path): 0.285ns (requirement - (clock path skew + uncertainty - data path))
  411. Source: simple_gemac_wrapper/flow_ctrl_rx/pause_req (FF)
  412. Destination: simple_gemac_wrapper/simple_gemac/simple_gemac_tx/pause_time_held_5 (FF)
  413. Requirement: 0.000ns
  414. Data Path Delay: 0.289ns (Levels of Logic = 0)
  415. Clock Path Skew: 0.004ns (0.065 - 0.061)
  416. Source Clock: clk_125 rising at 8.000ns
  417. Destination Clock: clk_125 rising at 8.000ns
  418. Clock Uncertainty: 0.000ns
  419.  
  420. Minimum Data Path at Fast Process Corner: simple_gemac_wrapper/flow_ctrl_rx/pause_req to simple_gemac_wrapper/simple_gemac/simple_gemac_tx/pause_time_held_5
  421. Location Delay type Delay(ns) Physical Resource
  422. Logical Resource(s)
  423. ------------------------------------------------- -------------------
  424. SLICE_X44Y72.AQ Tcko 0.234 simple_gemac_wrapper/flow_ctrl_rx/pause_req
  425. simple_gemac_wrapper/flow_ctrl_rx/pause_req
  426. SLICE_X44Y71.CE net (fanout=5) 0.157 simple_gemac_wrapper/flow_ctrl_rx/pause_req
  427. SLICE_X44Y71.CLK Tckce (-Th) 0.102 simple_gemac_wrapper/simple_gemac/simple_gemac_tx/pause_time_held<7>
  428. simple_gemac_wrapper/simple_gemac/simple_gemac_tx/pause_time_held_5
  429. ------------------------------------------------- ---------------------------
  430. Total 0.289ns (0.132ns logic, 0.157ns route)
  431. (45.7% logic, 54.3% route)
  432.  
  433. --------------------------------------------------------------------------------
  434.  
  435. Component Switching Limit Checks: TS_clk_125_tx_clkout0 = PERIOD TIMEGRP "clk_125_tx_clkout0" TS_clock * 1.25
  436. HIGH 50%;
  437. --------------------------------------------------------------------------------
  438. Slack: 4.876ns (period - min period limit)
  439. Period: 8.000ns
  440. Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
  441. Physical resource: simple_gemac_wrapper/tx_2clk_fifo/fifo_2clock/fifo_xlnx_64x36_2clk/BU2/U0/gconvfifo.rf/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK
  442. Logical resource: simple_gemac_wrapper/tx_2clk_fifo/fifo_2clock/fifo_xlnx_64x36_2clk/BU2/U0/gconvfifo.rf/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK
  443. Location pin: RAMB8_X2Y18.CLKAWRCLK
  444. Clock network: clk_125
  445. --------------------------------------------------------------------------------
  446. Slack: 4.876ns (period - min period limit)
  447. Period: 8.000ns
  448. Min period limit: 3.124ns (320.102MHz) (Trper_CLKB(Fmax))
  449. Physical resource: simple_gemac_wrapper/tx_2clk_fifo/fifo_2clock/fifo_xlnx_64x36_2clk/BU2/U0/gconvfifo.rf/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKBRDCLK
  450. Logical resource: simple_gemac_wrapper/tx_2clk_fifo/fifo_2clock/fifo_xlnx_64x36_2clk/BU2/U0/gconvfifo.rf/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKBRDCLK
  451. Location pin: RAMB8_X2Y18.CLKBRDCLK
  452. Clock network: clk_125
  453. --------------------------------------------------------------------------------
  454. Slack: 4.876ns (period - min period limit)
  455. Period: 8.000ns
  456. Min period limit: 3.124ns (320.102MHz) (Trper_CLKB(Fmax))
  457. Physical resource: simple_gemac_wrapper/rx_2clk_fifo/fifo_2clock/fifo_xlnx_512x36_2clk/BU2/U0/gconvfifo.rf/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKB
  458. Logical resource: simple_gemac_wrapper/rx_2clk_fifo/fifo_2clock/fifo_xlnx_512x36_2clk/BU2/U0/gconvfifo.rf/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKB
  459. Location pin: RAMB16_X1Y34.CLKB
  460. Clock network: clk_125
  461. --------------------------------------------------------------------------------
  462.  
  463.  
  464. Derived Constraint Report
  465. Derived Constraints for TS_clock
  466. +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
  467. | | Period | Actual Period | Timing Errors | Paths Analyzed |
  468. | Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
  469. | | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
  470. +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
  471. |TS_clock | 10.000ns| 6.431ns| 21.141ns| 0| 15777| 1701| 1220637|
  472. | TS_clk_125_tx_clkout1 | 8.000ns| 1.730ns| N/A| 0| 0| 0| 0|
  473. | TS_clk_125_tx_clkout0 | 8.000ns| 16.913ns| N/A| 15777| 0| 1220637| 0|
  474. +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
  475.  
  476. 1 constraint not met.
  477.  
  478.  
  479. Data Sheet report:
  480. -----------------
  481. All values displayed in nanoseconds (ns)
  482.  
  483. Clock to Setup on destination clock GMII_RX_CLK_pin
  484. ---------------+---------+---------+---------+---------+
  485. | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
  486. Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
  487. ---------------+---------+---------+---------+---------+
  488. GMII_RX_CLK_pin| 7.241| | | |
  489. ---------------+---------+---------+---------+---------+
  490.  
  491. Clock to Setup on destination clock clk_100_pin
  492. ---------------+---------+---------+---------+---------+
  493. | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
  494. Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
  495. ---------------+---------+---------+---------+---------+
  496. clk_100_pin | 16.913| | | |
  497. ---------------+---------+---------+---------+---------+
  498.  
  499.  
  500. Timing summary:
  501. ---------------
  502.  
  503. Timing errors: 15777 Score: 34840317 (Setup/Max: 34840317, Hold: 0)
  504.  
  505. Constraints cover 1228818 paths, 0 nets, and 110627 connections
  506.  
  507. Design statistics:
  508. Minimum period: 16.913ns{1} (Maximum frequency: 59.126MHz)
  509.  
  510.  
  511. ------------------------------------Footnotes-----------------------------------
  512. 1) The minimum period statistic assumes all single cycle delays.
  513.  
  514. Analysis completed Sun Jul 6 20:32:24 2014
  515. --------------------------------------------------------------------------------
  516.  
  517. Trace Settings:
  518. -------------------------
  519. Trace Settings
  520.  
  521. Peak Memory Usage: 823 MB
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