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  1. /*
  2.  * display.asm
  3.  *
  4.  *  Created: 23.11.2011 18:23:18
  5.  *   Author: Ondra Moravek
  6.  *   BOOTLOADER_NATIVE
  7.  */
  8.  
  9.  .def R_ROW = R6
  10.  .def R_VIEW = R2
  11.  .def R_BUFFER = R3
  12.  .def R_NBUFFER = R4 ; next buffer
  13.  
  14. .dseg
  15. .org 0xC000
  16.     BUFFER0: .byte 0x2000 ; 16 views 1 buffer... 16 views in total, each half kilobyte
  17.     /* Organization:
  18.         Buffer 0 (0xC000 - 0xDFFF)
  19.             View 0 (0xC000 - 0xC1FF)
  20.                 R 8pixel (0xC000 - 0xC001)
  21.                 G 8pixel (0xC001 - 0xC002)
  22.             View 1 (0xC200 - 0xC3FF)
  23.             ...
  24.             View 15 (0xDE00 - 0xDFFF)
  25.             ...
  26.     */
  27.     BUFFER1: .byte 0x2000 ; ... the same
  28. .cseg
  29.  
  30. DISPLAY_TIMER_INIT: ; inits the timers and such. NOT an interrupt driven!
  31.     LDI     R16, 0xFE ; output compare shall fire up right before the main timer ovf fires up...
  32.     OUT     OCR0, R16
  33.     LDI     R16, (1<<CS01)|(1<<CS00) ; clk/32
  34.     OUT     TCCR0, R16 ; timer is running now
  35.     LDI     R16, (1<<TOIE0)|(1<<OCIE0) ; setup interrupts
  36.     OUT     TIMSK, R16 ; interrupts enabled... but not the I flag yet!
  37.     RET
  38.  
  39.  
  40. DISPLAY_TIMER_CLEAR: ; just clear the first 595 so the output MOSFETs can discharge. Good enough is few us before the main timer fires up
  41.     PUSH    R16
  42.     IN      R16, SREG
  43.     PUSH    R16
  44.     ; disable display output..
  45.     DISPLAY_DISABLE
  46.     LDI     R16, 0xFF ; should disable both outputs... drive all MOSFETs high!
  47.     RCALL   SPI_Send
  48.     DISPLAY_TOGGLE_RCK
  49.     POP     R16
  50.     OUT     SREG, R16
  51.     POP     R16
  52.     RETI
  53.  
  54. DISPLAY_TIMER:
  55.     /* PUSH ORDER: R16, SREG, YL, YH, ZL, ZH, R0, R1, R17, R20, R21, R22, R23
  56.         Set new address pointer into Y register.
  57.         Formula: BUFFER+Buffer*<buffer size>+View*<view size>+<row>*<row size>, second one +. Row size = 10h (4bit boundary), view size = 10h*32 = 200h, buffer size = 200h*16 = 2000h
  58.         First run: <row> = row + 16, second run = row
  59.         last byte sent (25th) is row.
  60.         Then INC row
  61.         and last reset wdr
  62.     */
  63.     PUSH    R16
  64.     IN      R16, SREG
  65.     PUSH    R16
  66.     PUSH    YL
  67.     PUSH    YH
  68.     PUSH    ZL
  69.     PUSH    ZH
  70.     PUSH    R0
  71.     PUSH    R1
  72.     PUSH    R17
  73.     PUSH    R18
  74.     PUSH    R19
  75.     PUSH    R20
  76.     PUSH    R21
  77.     PUSH    R22
  78.     PUSH    R23
  79.         DISPLAY_ENABLE ; and enable display
  80.         SBI     PortB, PB0
  81.     TST     R_BUFFER
  82.     BREQ    DISPLAY_TIMER_B0
  83.     ; DISPLAY_TIMER_B1
  84.     LDI     YL, LOW(BUFFER1)
  85.     LDI     YH, HIGH(BUFFER1)
  86.     RJMP    DISPLAY_TIMER_VIEW
  87. DISPLAY_TIMER_B0:
  88.     LDI     YL, LOW(BUFFER0)
  89.     LDI     YH, HIGH(BUFFER0)
  90.    
  91. DISPLAY_TIMER_VIEW:
  92.     ANDI    GAME_IFACE_CR, (1<<GAME_IFACE_VEN)
  93.     BREQ    DISPLAY_TIMER_ROW ;skip if only one view is enabled
  94.     ; TODO: multiple views
  95.    
  96. DISPLAY_TIMER_ROW: ; add ROW. Remember that we start by (row+16)!
  97.     LDI     R16, 16
  98.     MOV     R17, R_ROW
  99.     ADD     R17, R16
  100.     ; okay, now we have the proper row number!
  101.  
  102.     ; continue with making this row number into address addition. One row = 12 bytes long, it is aligned to 16 bytes. Ergo << 4.
  103.     CLR     R18
  104.     LSL     R17
  105.     LSL     R17
  106.     LSL     R17
  107.     LSL     R17
  108.     ; if we were doing line 15 (ergo the last one), we have reached the end of 8bits, need to add 9th bit!
  109.     BRCC    DISPLAY_TIMER_ROW_CNT
  110.     ; we need the extra bit
  111.     LDI     R18, 0x01
  112. DISPLAY_TIMER_ROW_CNT:
  113.     ADD16   YH, YL, R18, R17
  114.  
  115.     ; okay, row # added. Now add another 12 so we accomodate the fact that we begin from the end. Actually it is 13, because we pre-decrement the Y ptr in the loop, no post decrement available
  116.     LDI     R17, 13
  117.     CLR     R18
  118.     ADD16   YH, YL, R18, R17
  119.  
  120.     ; now we have hopefuly the ending address. Start sending from the end, 12 bytes.
  121.     ;LDI        R17, 12
  122.  
  123. DISPLAY_TIMER_LOOP1:
  124.     LD      R16, -Y
  125.     RCALL   SPI_Send
  126.     DEC     R17
  127.     BREQ    DISPLAY_TIMER_LOOP2_SET ; all 12 bytes sent
  128.     RJMP    DISPLAY_TIMER_LOOP1
  129.  
  130. DISPLAY_TIMER_LOOP2_SET:
  131.     LDI     R17, 0xF3
  132.     LDI     R18, 0x00 ; minus 0x10 = 0xF5
  133.     SUB16   YH, YL, R18, R17
  134.  
  135.     LDI     R17, 13 ; loop timer
  136.  
  137. DISPLAY_TIMER_LOOP2:
  138.     LD      R16, -Y
  139.     RCALL   SPI_Send
  140.     DEC     R17
  141.     BREQ    DISPLAY_TIMER_SENT
  142.     RJMP    DISPLAY_TIMER_LOOP2
  143.  
  144. DISPLAY_TIMER_SENT: ; now take care about the row #
  145.     MOV     R16, R_ROW
  146.     RCALL   SPI_Send
  147.     DISPLAY_TOGGLE_RCK
  148.  
  149.     INC     R_ROW ; rise the row #
  150.     ;BRHS   DISPLAY_TIMER_VIEW_NEW ; if we're trying to switch to 16th line (counted from 0), nothx!
  151.     MOV     R16, R_ROW
  152.     CPI     R16, 16
  153.     BRGE    DISPLAY_TIMER_VIEW_NEW
  154.     RJMP    DISPLAY_TIMER_DONE
  155. DISPLAY_TIMER_VIEW_NEW:
  156.     CLR     R_ROW ; clear row #
  157.     INC     R_VIEW
  158.     ;BRHS   DISPLAY_TIMER_VIEW_OVF
  159.     MOV     R16, R_VIEW
  160.     CPI     R16, 16
  161.     BRGE    DISPLAY_TIMER_VIEW_OVF
  162.     RJMP    DISPLAY_TIMER_DONE
  163. DISPLAY_TIMER_VIEW_OVF:
  164.     MOV     R_BUFFER, R_NBUFFER ; copy new buffer #
  165.     CLR     R_VIEW ; clear view #
  166.  
  167. DISPLAY_TIMER_DONE:
  168.  
  169.     ; let's pop it all back
  170.     POP     R23
  171.     POP     R22
  172.     POP     R21
  173.     POP     R20
  174.     POP     R19
  175.     POP     R18
  176.     POP     R17
  177.     POP     R1
  178.     POP     R0
  179.     POP     ZH
  180.     POP     ZL
  181.     POP     YH
  182.     POP     YL
  183.     POP     R16
  184.     OUT     SREG, R16
  185.     POP     R16
  186.     WDR ; reset watchdog
  187.     RETI
  188.  
  189. DISPLAY_PWM_INIT: ; brightness PWM... reset (default) to 0 (aka completely shut... takes over safety after directly driving Display Enable pin to HIGH (active low, remember?)
  190.     LDI     R16, 0
  191.     OUT     OCR2, R16
  192.     LDI     R16, 0x71
  193.     OUT     TCCR2, R16
  194.     RET
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