module alu(input Clock, input Reset,
           input ClockEnable, input Flush,

           input [2:0] Op, input Fix, input Short,
           input [63:0] Ai, input [63:0] Bi,
           input [4:0] DestReg,

           output [63:0] Result,
           output [4:0] ResultReg);


  reg [5*8-1:0] RegDest;

  assign ResultReg = RegDest[5*7 +: 5];

  always @(posedge Clock)
  if(Reset || Flush)
  begin
    RegDest <= 0;
  end
  else if(ClockEnable)
  begin
    RegDest <= {RegDest[0 +: 7*5], DestReg};
  end

  wire [3*9-1:0] OpNext;
  wire [8:0] CarryIn;
  wire [64*9-1:0] A;
  wire [64*9-1:0] B;

  assign OpNext[2:0] = Op;
  assign CarryIn[0] = ((Op == 0) && Fix) ? 1'b1 :
                      ((Op == 5) && Fix) ? Ai[63] :
                      1'b0;
  assign A[63:0] = Ai;
  assign B[63:0] = ((Op == 0) && Fix) ? ~Bi : Bi;

  assign Result = A[64*8 +: 64];

  genvar i;
  generate
    for(i=0; i<8; i=i+1)
    begin : alu_stages
      alu_stage #(.STAGE(i)) stage(
        .Clock(Clock),
        .Reset(Reset),
        .ClockEnable(ClockEnable),
        .Op(OpNext[3*i +: 3]),
        .OpNext(OpNext[3*(i+1) +: 3]),
        .CarryIn(CarryIn[i]),
        .CarryOut(CarryIn[i+1]),
        .A(A[i*64 +: 64]),
        .B(B[i*64 +: 64]),
        .NextA(A[(i+1)*64 +: 64]),
        .NextB(B[(i+1)*64 +: 64])
      );
    end
  endgenerate

endmodule

module alu_stage #( parameter STAGE = 0 )
                (input Clock, input Reset,
                 input ClockEnable,

                 input [2:0] Op,
                 output reg [2:0] OpNext,

                 input CarryIn,
                 output reg CarryOut,
                 input [63:0] A, input [63:0] B,
                 output reg [63:0] NextA, output reg [63:0] NextB);

  // Stage 0: AS+Xor
  // Stage 4: AS+And
  // Stage 6: AS+Or

  wire [9:0] AddSubResult = {1'b0, A[STAGE*8 +: 8],CarryIn}+{1'b0, B[STAGE*8 +: 8],1'b1};

  wire [63:0] AddResult;
  wire [63:0] NeqResult;
  wire [63:0] XorResult;
  wire [63:0] AndResult;
  wire [63:0] OrResult;

  generate
    if(STAGE == 0)
      assign AddResult = {A[63:8], AddSubResult[8:1]};
    else if(STAGE == 7)
      assign AddResult = {AddSubResult[8:1], A[55:0]};
    else
      assign AddResult = {A[63:(STAGE+1)*8], AddSubResult[8:1], A[0 +: STAGE*8]};
  endgenerate

  wire [3*64-1:0] ShiftInput = {{64{CarryIn}}, A, 64'd0};
  wire [63:0] SllResult;
  wire [63:0] SrlResult;

  generate
    if(STAGE < 6) assign SllResult = B[STAGE] ? ShiftInput[64-(1<<STAGE) +: 64] : ShiftInput[64 +: 64];
    else assign SllResult = A;

    if(STAGE < 6) assign SrlResult = B[STAGE] ? ShiftInput[64+(1<<STAGE) +: 64] : ShiftInput[64 +: 64];
    else assign SrlResult = A;
  endgenerate

  generate
    if(STAGE == 0) assign NeqResult = A ^ B;
    else if(STAGE < 7) assign NeqResult = A | A[(1<<(STAGE-1)) +: (64-(1<<(STAGE-1)))];
    else assign NeqResult = {63'd0, A[0]};
  endgenerate

  generate
    if(STAGE == 0) assign XorResult = NeqResult;
    else assign XorResult = CarryIn ? NeqResult : A;
  endgenerate

  generate
    if(STAGE == 4) assign AndResult = A & B;
    else assign AndResult = A;
  endgenerate

  generate
    if(STAGE == 6) assign OrResult = A | B;
    else assign OrResult = A;
  endgenerate

  always @(posedge Clock)
    if(Reset)
    begin
      OpNext <= 0;
      NextA <= 0;
      NextB <= 0;
      CarryOut <= 0;
    end
    else if(ClockEnable)
    begin
      OpNext <= Op;

      NextA <= A;
      NextB <= B;

      CarryOut <= 1'b0;

      case(Op)
        0,2,3:
          begin
            NextA <= AddResult;
            CarryOut <= AddSubResult[9];
          end
        1: NextA <= SllResult;
        5:
          begin
            NextA <= SrlResult;
            CarryOut <= CarryIn;
          end
        4: NextA <= XorResult;
        6: NextA <= AndResult;
        7: NextA <= OrResult;
      endcase
    end

endmodule