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  1. /*
  2.  * Freescale ESAI ALSA SoC Digital Audio Interface (DAI) driver
  3.  *
  4.  * Copyright (C) 2014 Freescale Semiconductor, Inc.
  5.  *
  6.  * This file is licensed under the terms of the GNU General Public License
  7.  * version 2. This program is licensed "as is" without any warranty of any
  8.  * kind, whether express or implied.
  9.  */
  10.  
  11. #include <linux/clk.h>
  12. #include <linux/dmaengine.h>
  13. #include <linux/module.h>
  14. #include <linux/of_irq.h>
  15. #include <linux/of_platform.h>
  16. #include <sound/dmaengine_pcm.h>
  17. #include <sound/pcm_params.h>
  18.  
  19. #include "fsl_esai.h"
  20. #include "imx-pcm.h"
  21.  
  22. #define FSL_ESAI_RATES      SNDRV_PCM_RATE_8000_192000
  23. #define FSL_ESAI_FORMATS    (SNDRV_PCM_FMTBIT_S8 | \
  24.                 SNDRV_PCM_FMTBIT_S16_LE | \
  25.                 SNDRV_PCM_FMTBIT_S20_3LE | \
  26.                 SNDRV_PCM_FMTBIT_S24_LE)
  27.  
  28. #define pr_info_aurel
  29.  
  30. #define ESAI_DUMP() \
  31.     do {u32 val;pr_info_aurel("dump @ %s\n", __func__); \
  32.     regmap_read(esai_priv->regmap, REG_ESAI_ECR, &val);pr_info_aurel("ESAI_ECR   0x%08x\n", val); \
  33.     regmap_read(esai_priv->regmap, REG_ESAI_ESR, &val);pr_info_aurel("ESAI_ESR   0x%08x\n", val); \
  34.     regmap_read(esai_priv->regmap, REG_ESAI_TFCR, &val);pr_info_aurel("ESAI_TFCR  0x%08x\n", val); \
  35.     regmap_read(esai_priv->regmap, REG_ESAI_TFSR, &val);pr_info_aurel("ESAI_TFSR  0x%08x\n", val); \
  36.     regmap_read(esai_priv->regmap, REG_ESAI_RFCR, &val);pr_info_aurel("ESAI_RFCR  0x%08x\n", val); \
  37.     regmap_read(esai_priv->regmap, REG_ESAI_RFSR, &val);pr_info_aurel("ESAI_RFSR  0x%08x\n", val); \
  38.     regmap_read(esai_priv->regmap, REG_ESAI_TSR, &val);pr_info_aurel("ESAI_TSR   0x%08x\n", val); \
  39.     regmap_read(esai_priv->regmap, REG_ESAI_SAISR, &val);pr_info_aurel("ESAI_SAISR 0x%08x\n", val); \
  40.     regmap_read(esai_priv->regmap, REG_ESAI_SAICR, &val);pr_info_aurel("ESAI_SAICR 0x%08x\n", val); \
  41.     regmap_read(esai_priv->regmap, REG_ESAI_TCR, &val);pr_info_aurel("ESAI_TCR   0x%08x\n", val); \
  42.     regmap_read(esai_priv->regmap, REG_ESAI_TCCR, &val);pr_info_aurel("ESAI_TCCR  0x%08x\n", val); \
  43.     regmap_read(esai_priv->regmap, REG_ESAI_RCR, &val);pr_info_aurel("ESAI_RCR   0x%08x\n", val); \
  44.     regmap_read(esai_priv->regmap, REG_ESAI_RCCR, &val);pr_info_aurel("ESAI_RCCR  0x%08x\n", val); \
  45.     regmap_read(esai_priv->regmap, REG_ESAI_TSMA, &val);pr_info_aurel("ESAI_TSMA  0x%08x\n", val); \
  46.     regmap_read(esai_priv->regmap, REG_ESAI_TSMB, &val);pr_info_aurel("ESAI_TSMB  0x%08x\n", val); \
  47.     regmap_read(esai_priv->regmap, REG_ESAI_RSMA, &val);pr_info_aurel("ESAI_RSMA  0x%08x\n", val); \
  48.     regmap_read(esai_priv->regmap, REG_ESAI_RSMB, &val);pr_info_aurel("ESAI_RSMB  0x%08x\n", val); \
  49.     regmap_read(esai_priv->regmap, REG_ESAI_PRRC, &val);pr_info_aurel("ESAI_PRRC  0x%08x\n", val); \
  50.     regmap_read(esai_priv->regmap, REG_ESAI_PCRC, &val);pr_info_aurel("ESAI_PCRC  0x%08x\n", val); \
  51.     } while (0);
  52.  
  53.  
  54.  
  55. /**
  56.  * fsl_esai: ESAI private data
  57.  *
  58.  * @dma_params_rx: DMA parameters for receive channel
  59.  * @dma_params_tx: DMA parameters for transmit channel
  60.  * @pdev: platform device pointer
  61.  * @regmap: regmap handler
  62.  * @coreclk: clock source to access register
  63.  * @extalclk: esai clock source to derive HCK, SCK and FS
  64.  * @fsysclk: system clock source to derive HCK, SCK and FS
  65.  * @fifo_depth: depth of tx/rx FIFO
  66.  * @slot_width: width of each DAI slot
  67.  * @hck_rate: clock rate of desired HCKx clock
  68.  * @sck_div: if using PSR/PM dividers for SCKx clock
  69.  * @slave_mode: if fully using DAI slave mode
  70.  * @synchronous: if using tx/rx synchronous mode
  71.  * @name: driver name
  72.  */
  73. struct fsl_esai {
  74.     struct snd_dmaengine_dai_dma_data dma_params_rx;
  75.     struct snd_dmaengine_dai_dma_data dma_params_tx;
  76.     struct imx_dma_data filter_data_tx;
  77.     struct imx_dma_data filter_data_rx;
  78.     struct snd_pcm_substream *substream[2];
  79.     struct platform_device *pdev;
  80.     struct regmap *regmap;
  81.     struct clk *coreclk;
  82.     struct clk *extalclk;
  83.     struct clk *fsysclk;
  84.     struct clk *dmaclk;
  85.     u32 fifo_depth;
  86.     u32 slot_width;
  87.     u32 slots;
  88.     u32 tx_mask;
  89.     u32 rx_mask;
  90.     u32 hck_rate[2];
  91.     bool sck_div[2];
  92.     bool slave_mode;
  93.     bool synchronous;
  94.     char name[32];
  95. };
  96.  
  97. static irqreturn_t esai_isr(int irq, void *devid)
  98. {
  99.     struct fsl_esai *esai_priv = (struct fsl_esai *)devid;
  100.     struct platform_device *pdev = esai_priv->pdev;
  101.     u32 esr;
  102.  
  103.     regmap_read(esai_priv->regmap, REG_ESAI_ESR, &esr);
  104.  
  105.     if (esr & ESAI_ESR_TINIT_MASK)
  106.         dev_dbg(&pdev->dev, "isr: Transmition Initialized\n");
  107.  
  108.     if (esr & ESAI_ESR_RFF_MASK)
  109.         dev_warn(&pdev->dev, "isr: Receiving overrun\n");
  110.  
  111.     if (esr & ESAI_ESR_TFE_MASK)
  112.         dev_warn(&pdev->dev, "isr: Transmition underrun\n");
  113.  
  114.     if (esr & ESAI_ESR_TLS_MASK)
  115.         dev_dbg(&pdev->dev, "isr: Just transmitted the last slot\n");
  116.  
  117.     if (esr & ESAI_ESR_TDE_MASK)
  118.         dev_dbg(&pdev->dev, "isr: Transmition data exception\n");
  119.  
  120.     if (esr & ESAI_ESR_TED_MASK)
  121.         dev_dbg(&pdev->dev, "isr: Transmitting even slots\n");
  122.  
  123.     if (esr & ESAI_ESR_TD_MASK)
  124.         dev_dbg(&pdev->dev, "isr: Transmitting data\n");
  125.  
  126.     if (esr & ESAI_ESR_RLS_MASK)
  127.         dev_dbg(&pdev->dev, "isr: Just received the last slot\n");
  128.  
  129.     if (esr & ESAI_ESR_RDE_MASK)
  130.         dev_dbg(&pdev->dev, "isr: Receiving data exception\n");
  131.  
  132.     if (esr & ESAI_ESR_RED_MASK)
  133.         dev_dbg(&pdev->dev, "isr: Receiving even slots\n");
  134.  
  135.     if (esr & ESAI_ESR_RD_MASK)
  136.         dev_dbg(&pdev->dev, "isr: Receiving data\n");
  137.  
  138.     return IRQ_HANDLED;
  139. }
  140.  
  141. /**
  142.  * This function is used to calculate the divisors of psr, pm, fp and it is
  143.  * supposed to be called in set_dai_sysclk() and set_bclk().
  144.  *
  145.  * @ratio: desired overall ratio for the paticipating dividers
  146.  * @usefp: for HCK setting, there is no need to set fp divider
  147.  * @fp: bypass other dividers by setting fp directly if fp != 0
  148.  * @tx: current setting is for playback or capture
  149.  */
  150. static int fsl_esai_divisor_cal(struct snd_soc_dai *dai, bool tx, u32 ratio,
  151.                 bool usefp, u32 fp)
  152. {
  153.     struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
  154.     u32 psr, pm = 999, maxfp, prod, sub, savesub, i, j;
  155.  
  156.     maxfp = usefp ? 16 : 1;
  157.  
  158.     if (usefp && fp)
  159.         goto out_fp;
  160.  
  161.     if (ratio > 2 * 8 * 256 * maxfp || ratio < 2) {
  162.         dev_err(dai->dev, "the ratio is out of range (2 ~ %d)\n",
  163.                 2 * 8 * 256 * maxfp);
  164.         return -EINVAL;
  165.     } else if (ratio % 2) {
  166.         dev_err(dai->dev, "the ratio must be even if using upper divider\n");
  167.         return -EINVAL;
  168.     }
  169.     pr_info_aurel("ratio:%d\n",ratio);
  170.     ratio /= 2;
  171.  
  172.     psr = ratio <= 256 * maxfp ? ESAI_xCCR_xPSR_BYPASS : ESAI_xCCR_xPSR_DIV8;
  173.     if(psr){
  174.         /* Set the max fluctuation -- 1% of the max divisor */
  175.         savesub = 1  * 256 * maxfp / 100;
  176.     }else{
  177.         /* Set the max fluctuation -- 0.1% of the max divisor */
  178.         savesub = 8  * 256 * maxfp / 1000;
  179.     }
  180.     pr_info_aurel("init savesub:%d\n",savesub);
  181.  
  182.     /* Find the best value for PM */
  183.     for (i = 1; i <= 256; i++) {
  184.         for (j = 1; j <= maxfp; j++) {
  185.             /* PSR (1 or 8) * PM (1 ~ 256) * FP (1 ~ 16) */
  186.             pr_info_aurel("psr ret:%d;i:%d;j:%d\n",(psr ? 1 : 8),i,j);
  187.             prod = (psr ? 1 : 8) * i * j;
  188.             pr_info_aurel("prod:%d\n",prod);
  189.  
  190.             if (prod == ratio)
  191.                 sub = 0;
  192.             else if (prod / ratio == 1)
  193.                 sub = prod - ratio;
  194.             else if (ratio / prod == 1)
  195.                 sub = ratio - prod;
  196.             else
  197.                 continue;
  198.  
  199.             /* Calculate the fraction */
  200.             pr_info_aurel("(%d)sub:%d\n",__LINE__,sub);
  201.             sub = sub * 1000 / ratio;
  202.             pr_info_aurel("(%d)sub:%d\n",__LINE__,sub);
  203.             if (sub < savesub) {
  204.                 savesub = sub;
  205.                 pm = i;
  206.                 fp = j;
  207.             }
  208.             pr_info_aurel("savesub:%d\n",savesub);
  209.             pr_info_aurel("pm:%d\n",pm);
  210.             pr_info_aurel("fp:%d\n",fp);
  211.  
  212.             /* We are lucky */
  213.             if (savesub == 0)
  214.                 goto out;
  215.         }
  216.     }
  217.  
  218.     if (pm == 999) {
  219.         dev_err(dai->dev, "failed to calculate proper divisors\n");
  220.         return -EINVAL;
  221.     }
  222.  
  223. out:
  224.     pr_info_aurel("Setting PM:%d=>0x%x\n",pm,pm);
  225.     regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
  226.                ESAI_xCCR_xPSR_MASK | ESAI_xCCR_xPM_MASK,
  227.                psr | ESAI_xCCR_xPM(pm));
  228.  
  229. out_fp:
  230.     /* Bypass fp if not being required */
  231.     if (maxfp <= 1)
  232.         return 0;
  233.  
  234.     pr_info_aurel("Setting FP:%d=>0x%x\n",fp,fp);
  235.     regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
  236.                ESAI_xCCR_xFP_MASK, ESAI_xCCR_xFP(fp));
  237.  
  238.     return 0;
  239. }
  240.  
  241. /**
  242.  * This function mainly configures the clock frequency of MCLK (HCKT/HCKR)
  243.  *
  244.  * @Parameters:
  245.  * clk_id: The clock source of HCKT/HCKR
  246.  *    (Input from outside; output from inside, FSYS or EXTAL)
  247.  * freq: The required clock rate of HCKT/HCKR
  248.  * dir: The clock direction of HCKT/HCKR
  249.  *
  250.  * Note: If the direction is input, we do not care about clk_id.
  251.  */
  252. static int fsl_esai_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
  253.                    unsigned int freq, int dir)
  254. {
  255.     struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
  256.     struct clk *clksrc = esai_priv->extalclk;
  257.     bool tx = clk_id <= ESAI_HCKT_EXTAL;
  258.     bool in = dir == SND_SOC_CLOCK_IN;
  259.     u32 ret, ratio, ecr = 0;
  260.     unsigned long clk_rate;
  261.  
  262.     /* sck_div can be only bypassed if ETO/ERO=0 and SNC_SOC_CLOCK_OUT */
  263.     esai_priv->sck_div[tx] = true;
  264.  
  265.     /* Set the direction of HCKT/HCKR pins */
  266.     regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
  267.                ESAI_xCCR_xHCKD, in ? 0 : ESAI_xCCR_xHCKD);
  268.  
  269.     if (in)
  270.         goto out;
  271.  
  272.     switch (clk_id) {
  273.     case ESAI_HCKT_FSYS:
  274.     case ESAI_HCKR_FSYS:
  275.         clksrc = esai_priv->fsysclk;
  276.         break;
  277.     case ESAI_HCKT_EXTAL:
  278.         ecr |= ESAI_ECR_ETI;
  279.     case ESAI_HCKR_EXTAL:
  280.         ecr |= ESAI_ECR_ERI;
  281.         break;
  282.     default:
  283.         return -EINVAL;
  284.     }
  285.  
  286.     if (IS_ERR(clksrc)) {
  287.         dev_err(dai->dev, "no assigned %s clock\n",
  288.                 clk_id % 2 ? "extal" : "fsys");
  289.         return PTR_ERR(clksrc);
  290.     }
  291.     clk_rate = clk_get_rate(clksrc);
  292.  
  293.     ratio = clk_rate;
  294.     ratio = DIV_ROUND_CLOSEST(ratio,freq);
  295.     pr_info_aurel("FYI clk_rate:%ld from %s ; freq:%d; ratio:%d\n",clk_rate,clk_id % 2 ? "extal" : "fsys",freq,ratio);
  296.     if (ratio * freq > clk_rate){
  297.         ret = ratio * freq - clk_rate;
  298.     }
  299.     else if (ratio * freq < clk_rate){
  300.         ret = clk_rate - ratio * freq;
  301.     }
  302.     else
  303.         ret = 0;
  304.  
  305.     pr_info_aurel("There is difference of %ld Hz between the one you need %d and the one you could get %ld \n",freq-clk_rate/ratio,freq,clk_rate/ratio);
  306.     /* Block if clock source can not be divided into the required rate */
  307.     if (ret != 0 && clk_rate / ret < 1000) {
  308.         dev_err(dai->dev, "failed to derive required HCK%c rate\n",
  309.                 tx ? 'T' : 'R');
  310.         return -EINVAL;
  311.     }
  312.  
  313.     if (ratio == 1) {
  314.         /* Bypass all the dividers if not being needed */
  315.         ecr |= tx ? ESAI_ECR_ETO : ESAI_ECR_ERO;
  316.         goto out;
  317.     }
  318.  
  319.     ret = fsl_esai_divisor_cal(dai, tx, ratio, false, 0);
  320.     if (ret)
  321.         return ret;
  322.  
  323.     esai_priv->sck_div[tx] = false;
  324.  
  325. out:
  326.     esai_priv->hck_rate[tx] = freq;
  327.  
  328.     regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,
  329.                tx ? ESAI_ECR_ETI | ESAI_ECR_ETO :
  330.                ESAI_ECR_ERI | ESAI_ECR_ERO, ecr);
  331.  
  332.     return 0;
  333. }
  334.  
  335. /**
  336.  * This function configures the related dividers according to the bclk rate
  337.  */
  338. static int fsl_esai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
  339. {
  340.     struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
  341.     u32 hck_rate = esai_priv->hck_rate[tx];
  342.     u32 sub, ratio;
  343.  
  344.     ratio = hck_rate;
  345.     ratio = DIV_ROUND_CLOSEST(ratio,freq);
  346.  
  347.     pr_info_aurel("%s we have hck_rate:%d\n",__func__,hck_rate);
  348.     /* Don't apply for fully slave mode*/
  349.     if (esai_priv->slave_mode)
  350.         return 0;
  351.  
  352.     if (ratio * freq > hck_rate)
  353.         sub = ratio * freq - hck_rate;
  354.     else if (ratio * freq < hck_rate)
  355.         sub = hck_rate - ratio * freq;
  356.     else
  357.         sub = 0;
  358.  
  359.  
  360.     if(sub){
  361.         pr_info_aurel("%s we sub:%d hck_rate/sub:%d \n",__func__,sub,(hck_rate / sub));
  362.         pr_info_aurel("There is difference of %d Hz between the one you need %d and the one you could get %d \n",sub,freq,hck_rate/ratio);
  363.     }
  364.  
  365.     /* Block if clock source can not be divided into the required rate */
  366.     if (sub != 0 && hck_rate / sub < 1000) {
  367.         dev_err(dai->dev, "failed to derive required SCK%c rate\n",
  368.                 tx ? 'T' : 'R');
  369.         return -EINVAL;
  370.     }
  371.  
  372.     if (esai_priv->sck_div[tx] && (ratio > 16 || ratio == 0)) {
  373.         dev_err(dai->dev, "the ratio is out of range (1 ~ 16)\n");
  374.         return -EINVAL;
  375.     }
  376.  
  377.     return fsl_esai_divisor_cal(dai, tx, ratio, true,
  378.             esai_priv->sck_div[tx] ? 0 : ratio);
  379. }
  380.  
  381. static int fsl_esai_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask,
  382.                      u32 rx_mask, int slots, int slot_width)
  383. {
  384.     struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
  385.  
  386.     regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR,
  387.                ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots));
  388. #if 0
  389.     regmap_update_bits(esai_priv->regmap, REG_ESAI_TSMA,
  390.                ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(tx_mask));
  391.     regmap_update_bits(esai_priv->regmap, REG_ESAI_TSMB,
  392.                ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(tx_mask));
  393. #endif
  394.     regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,
  395.                ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots));
  396. #if 0
  397.     regmap_update_bits(esai_priv->regmap, REG_ESAI_RSMA,
  398.                ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(rx_mask));
  399.     regmap_update_bits(esai_priv->regmap, REG_ESAI_RSMB,
  400.                ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(rx_mask));
  401. #endif
  402.     esai_priv->slot_width = slot_width;
  403.     esai_priv->slots      = slots;
  404.     esai_priv->tx_mask    = tx_mask;
  405.     esai_priv->rx_mask    = rx_mask;
  406.     ESAI_DUMP();
  407.     return 0;
  408. }
  409.  
  410. static int fsl_esai_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  411. {
  412.     struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
  413.     u32 xcr = 0, xccr = 0, mask;
  414.  
  415.     pr_info_aurel("%s(%d)\n",__func__,__LINE__);
  416.     /* DAI mode */
  417.     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  418.     case SND_SOC_DAIFMT_I2S:
  419.         /* Data on rising edge of bclk, frame low, 1clk before data */
  420.         xcr |= ESAI_xCR_xFSR;
  421.         xccr |= ESAI_xCCR_xFSP | ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
  422.         break;
  423.     case SND_SOC_DAIFMT_LEFT_J:
  424.         /* Data on rising edge of bclk, frame high */
  425.         xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
  426.         break;
  427.     case SND_SOC_DAIFMT_RIGHT_J:
  428.         /* Data on rising edge of bclk, frame high, right aligned */
  429.         xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCR_xWA;
  430.         break;
  431.     case SND_SOC_DAIFMT_DSP_A:
  432.         /* Data on rising edge of bclk, frame high, 1clk before data */
  433.         xcr |= ESAI_xCR_xFSL | ESAI_xCR_xFSR;
  434.         xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
  435.         break;
  436.     case SND_SOC_DAIFMT_DSP_B:
  437.         /* Data on rising edge of bclk, frame high */
  438.         xcr |= ESAI_xCR_xFSL;
  439.         xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
  440.         break;
  441.     default:
  442.         return -EINVAL;
  443.     }
  444.     pr_info_aurel("%s(%d)\n",__func__,__LINE__);
  445.     /* DAI clock inversion */
  446.     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  447.     case SND_SOC_DAIFMT_NB_NF:
  448.         /* Nothing to do for both normal cases */
  449.         break;
  450.     case SND_SOC_DAIFMT_IB_NF:
  451.         /* Invert bit clock */
  452.         xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
  453.         break;
  454.     case SND_SOC_DAIFMT_NB_IF:
  455.         /* Invert frame clock */
  456.         xccr ^= ESAI_xCCR_xFSP;
  457.         break;
  458.     case SND_SOC_DAIFMT_IB_IF:
  459.         /* Invert both clocks */
  460.         xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP;
  461.         break;
  462.     default:
  463.         return -EINVAL;
  464.     }
  465.     pr_info_aurel("%s(%d)\n",__func__,__LINE__);
  466.     esai_priv->slave_mode = false;
  467.  
  468.     /* DAI clock master masks */
  469.     switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  470.     case SND_SOC_DAIFMT_CBM_CFM:
  471.         esai_priv->slave_mode = true;
  472.         break;
  473.     case SND_SOC_DAIFMT_CBS_CFM:
  474.         xccr |= ESAI_xCCR_xCKD;
  475.         break;
  476.     case SND_SOC_DAIFMT_CBM_CFS:
  477.         xccr |= ESAI_xCCR_xFSD;
  478.         break;
  479.     case SND_SOC_DAIFMT_CBS_CFS:
  480.         xccr |= ESAI_xCCR_xFSD | ESAI_xCCR_xCKD;
  481.         break;
  482.     default:
  483.         return -EINVAL;
  484.     }
  485.  
  486.     mask = ESAI_xCR_xFSL | ESAI_xCR_xFSR;
  487.  
  488. //#define MAKE_TCR_INTERRUPTIBLE
  489. #ifdef MAKE_TCR_INTERRUPTIBLE
  490.     //make it interruptible
  491.     pr_info_aurel("%s(%d)\n",__func__,__LINE__);
  492.     mask |= ESAI_xCR_xEIE_MASK | ESAI_xCR_xIE_MASK;
  493.     xcr |= ESAI_xCR_xEIE | ESAI_xCR_xIE;
  494.     //make it interruptible
  495. #endif /* MAKE_TCR_INTERRUPTIBLE */
  496. #ifdef MAKE_TRANSMIT_LAST_SLOT_INT
  497.     mask |= ESAI_xCR_xLIE_MASK;
  498.     xcr |= ESAI_xCR_xLIE;
  499. #endif /* MAKE_TRANSMIT_LAST_SLOT_INT */
  500. #ifdef MAKE_TRANSMIT_EVEN_SLOT_INT
  501.     mask |= ESAI_xCR_xEDIE_MASK;
  502.     xcr |= ESAI_xCR_xEDIE;
  503. #endif /* MAKE_TRANSMIT_EVEN_SLOT_INT */
  504. //#define FRAME_SYNCHRO_1_BIT
  505. #ifdef FRAME_SYNCHRO_1_BIT
  506.     mask |= ESAI_xCR_xFSL_MASK;
  507.     xcr |= ESAI_xCR_xFSL;
  508. #endif /* FRAME_SYNCHRO_1_BIT */
  509.  
  510.     pr_info_aurel("xcr:0x%0X\n",xcr);
  511.     regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, xcr);
  512.     regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, mask, xcr);
  513.  
  514.     mask = ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP |
  515.         ESAI_xCCR_xFSD | ESAI_xCCR_xCKD | ESAI_xCR_xWA;
  516.     regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, mask, xccr);
  517.     regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, mask, xccr);
  518.     ESAI_DUMP();
  519.     return 0;
  520. }
  521.  
  522. static int fsl_esai_startup(struct snd_pcm_substream *substream,
  523.                 struct snd_soc_dai *dai)
  524. {
  525.     struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
  526.  
  527.     /*
  528.      * Some platforms might use the same bit to gate all three or two of
  529.      * clocks, so keep all clocks open/close at the same time for safety
  530.      */
  531.     clk_prepare_enable(esai_priv->dmaclk);
  532.     clk_prepare_enable(esai_priv->coreclk);
  533.     if (!IS_ERR(esai_priv->extalclk))
  534.         clk_prepare_enable(esai_priv->extalclk);
  535.     if (!IS_ERR(esai_priv->fsysclk))
  536.         clk_prepare_enable(esai_priv->fsysclk);
  537.  
  538.     if (!dai->active) {
  539.         /* Set synchronous mode */
  540.         regmap_update_bits(esai_priv->regmap, REG_ESAI_SAICR,
  541.                    ESAI_SAICR_SYNC, esai_priv->synchronous ?
  542.                    ESAI_SAICR_SYNC : 0);
  543.  
  544.         /* Set a default slot number -- 2 */
  545.         regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR,
  546.                    ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(2));
  547.         regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,
  548.                    ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(2));
  549.     }
  550.  
  551.     esai_priv->substream[substream->stream] = substream;
  552.  
  553.     return 0;
  554. }
  555.  
  556. static int fsl_esai_hw_params(struct snd_pcm_substream *substream,
  557.                   struct snd_pcm_hw_params *params,
  558.                   struct snd_soc_dai *dai)
  559. {
  560.     struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
  561.     bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
  562.     u32 width = snd_pcm_format_width(params_format(params));
  563.     u32 channels = params_channels(params);
  564.     u32 pin = DIV_ROUND_UP(channels, esai_priv->slots);
  565.     u32 bclk, mask, val, ret;
  566.  
  567.     bclk = params_rate(params) * esai_priv->slot_width * esai_priv->slots;
  568.  
  569.     ret = fsl_esai_set_bclk(dai, tx, bclk);
  570.     if (ret)
  571.         return ret;
  572.  
  573.     /* Use Normal mode to support monaural audio */
  574.     regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
  575.                ESAI_xCR_xMOD_MASK, ESAI_xCR_xMOD_NETWORK);//TODO : check if network mode with one channel
  576.     printk(KERN_ERR"using network mode\n");
  577.     regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
  578.                ESAI_xFCR_xFR_MASK, ESAI_xFCR_xFR);
  579.  
  580.     mask = ESAI_xFCR_xFR_MASK | ESAI_xFCR_xWA_MASK | ESAI_xFCR_xFWM_MASK |
  581.           (tx ? ESAI_xFCR_TE_MASK | ESAI_xFCR_TIEN : ESAI_xFCR_RE_MASK);
  582.     val = ESAI_xFCR_xWA(width) | ESAI_xFCR_xFWM(esai_priv->fifo_depth) |
  583.          (tx ? ESAI_xFCR_TE(pin) | ESAI_xFCR_TIEN : ESAI_xFCR_RE(pin));
  584.  
  585.     regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), mask, val);
  586.  
  587.     mask = ESAI_xCR_xSWS_MASK | (tx ? ESAI_xCR_PADC : 0);
  588.     val = ESAI_xCR_xSWS(esai_priv->slot_width, width) | (tx ? ESAI_xCR_PADC : 0);
  589.  
  590.     regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), mask, val);
  591.  
  592.     /* Reset Port C */
  593.     regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,
  594.                    ESAI_PRRC_PDC_MASK, ESAI_PRRC_PDC(ESAI_GPIO));
  595.     regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,
  596.                    ESAI_PCRC_PC_MASK, ESAI_PCRC_PC(ESAI_GPIO));
  597.  
  598.     printk(KERN_ERR"slot_width:%d\n",esai_priv->slot_width);
  599.     printk(KERN_ERR"snd_pcm_format_width:%d\n",width);
  600.     printk(KERN_ERR"params_channels:%d\n",channels);
  601.     printk(KERN_ERR"pins used:%d\n",pin);
  602.     printk(KERN_ERR"bclk:%d\n",bclk);
  603.     printk(KERN_ERR"network:%d\n",1);
  604.     printk(KERN_ERR"rate:%d\n",params_rate(params));
  605.     printk(KERN_ERR"fifo_depth:%d\n",esai_priv->fifo_depth);
  606.  
  607.     ESAI_DUMP();
  608.  
  609.     return 0;
  610. }
  611.  
  612. static void fsl_esai_shutdown(struct snd_pcm_substream *substream,
  613.                   struct snd_soc_dai *dai)
  614. {
  615.     struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
  616.  
  617.     if (!dai->active) {
  618.         /* Reset Port C */
  619.         regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,
  620.                    ESAI_PRRC_PDC_MASK, 0);
  621.         regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,
  622.                    ESAI_PCRC_PC_MASK, 0);
  623.     }
  624.  
  625.     esai_priv->substream[substream->stream] = NULL;
  626.  
  627.     if (!IS_ERR(esai_priv->fsysclk))
  628.         clk_disable_unprepare(esai_priv->fsysclk);
  629.     if (!IS_ERR(esai_priv->extalclk))
  630.         clk_disable_unprepare(esai_priv->extalclk);
  631.     clk_disable_unprepare(esai_priv->coreclk);
  632.     clk_disable_unprepare(esai_priv->dmaclk);
  633. }
  634.  
  635. static int fsl_esai_trigger(struct snd_pcm_substream *substream, int cmd,
  636.                 struct snd_soc_dai *dai)
  637. {
  638.     struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
  639.     bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
  640.     u8 i, channels = substream->runtime->channels;
  641.     u32 pin = DIV_ROUND_UP(channels, esai_priv->slots);
  642.     u32 mask;
  643.  
  644.     switch (cmd) {
  645.     case SNDRV_PCM_TRIGGER_START:
  646.     case SNDRV_PCM_TRIGGER_RESUME:
  647.     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  648.         regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
  649.                    ESAI_xFCR_xFEN_MASK, ESAI_xFCR_xFEN);
  650.  
  651.         /* Write initial words required by ESAI as normal procedure */
  652.         for (i = 0; tx && i < channels; i++)
  653.             regmap_write(esai_priv->regmap, REG_ESAI_ETDR, 0x0);
  654.  
  655.         regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
  656.                    tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK,
  657.                    tx ? ESAI_xCR_TE(pin) : ESAI_xCR_RE(pin));
  658.         mask = tx ? esai_priv->tx_mask : esai_priv->rx_mask;
  659.         regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx),
  660.                    ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(mask));
  661.         regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx),
  662.                    ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(mask));
  663.  
  664.         break;
  665.     case SNDRV_PCM_TRIGGER_SUSPEND:
  666.     case SNDRV_PCM_TRIGGER_STOP:
  667.     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  668.         regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
  669.                    tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, 0);
  670.         regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx),
  671.                    ESAI_xSMA_xS_MASK, 0);
  672.         regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx),
  673.                    ESAI_xSMB_xS_MASK, 0);
  674.  
  675.         /* Disable and reset FIFO */
  676.         regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
  677.                    ESAI_xFCR_xFR | ESAI_xFCR_xFEN, ESAI_xFCR_xFR);
  678.         regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
  679.                    ESAI_xFCR_xFR, 0);
  680.         break;
  681.     default:
  682.         return -EINVAL;
  683.     }
  684.  
  685.     ESAI_DUMP();
  686.     return 0;
  687. }
  688.  
  689. static struct snd_soc_dai_ops fsl_esai_dai_ops = {
  690.     .startup = fsl_esai_startup,
  691.     .shutdown = fsl_esai_shutdown,
  692.     .trigger = fsl_esai_trigger,
  693.     .hw_params = fsl_esai_hw_params,
  694.     .set_sysclk = fsl_esai_set_dai_sysclk,
  695.     .set_fmt = fsl_esai_set_dai_fmt,
  696.     .set_tdm_slot = fsl_esai_set_dai_tdm_slot,
  697. };
  698.  
  699. static int fsl_esai_dai_probe(struct snd_soc_dai *dai)
  700. {
  701.     struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
  702.  
  703.     snd_soc_dai_init_dma_data(dai, &esai_priv->dma_params_tx,
  704.                   &esai_priv->dma_params_rx);
  705.  
  706.     return 0;
  707. }
  708.  
  709. static struct snd_soc_dai_driver fsl_esai_dai = {
  710.     .probe = fsl_esai_dai_probe,
  711.     .playback = {
  712.         .stream_name = "esai-Playback",
  713.         .channels_min = 1,
  714.         .channels_max = 64,//12,
  715.         .rates = FSL_ESAI_RATES,
  716.         .formats = FSL_ESAI_FORMATS,
  717.     },
  718.     .capture = {
  719.         .stream_name = "esai-Capture",
  720.         .channels_min = 1,
  721.         .channels_max = 64,//8,
  722.         .rates = FSL_ESAI_RATES,
  723.         .formats = FSL_ESAI_FORMATS,
  724.     },
  725.     .ops = &fsl_esai_dai_ops,
  726. };
  727.  
  728. static const struct snd_soc_component_driver fsl_esai_component = {
  729.     .name       = "fsl-esai",
  730. };
  731.  
  732. static bool fsl_esai_readable_reg(struct device *dev, unsigned int reg)
  733. {
  734.     switch (reg) {
  735.     case REG_ESAI_ERDR:
  736.     case REG_ESAI_ECR:
  737.     case REG_ESAI_ESR:
  738.     case REG_ESAI_TFCR:
  739.     case REG_ESAI_TFSR:
  740.     case REG_ESAI_RFCR:
  741.     case REG_ESAI_RFSR:
  742.     case REG_ESAI_RX0:
  743.     case REG_ESAI_RX1:
  744.     case REG_ESAI_RX2:
  745.     case REG_ESAI_RX3:
  746.     case REG_ESAI_SAISR:
  747.     case REG_ESAI_SAICR:
  748.     case REG_ESAI_TCR:
  749.     case REG_ESAI_TCCR:
  750.     case REG_ESAI_RCR:
  751.     case REG_ESAI_RCCR:
  752.     case REG_ESAI_TSMA:
  753.     case REG_ESAI_TSMB:
  754.     case REG_ESAI_RSMA:
  755.     case REG_ESAI_RSMB:
  756.     case REG_ESAI_PRRC:
  757.     case REG_ESAI_PCRC:
  758.         return true;
  759.     default:
  760.         return false;
  761.     }
  762. }
  763.  
  764. static bool fsl_esai_volatile_reg(struct device *dev, unsigned int reg)
  765. {
  766.     switch (reg) {
  767.     case REG_ESAI_ETDR:
  768.     case REG_ESAI_ERDR:
  769.     case REG_ESAI_ESR:
  770.     case REG_ESAI_TFSR:
  771.     case REG_ESAI_RFSR:
  772.     case REG_ESAI_TX0:
  773.     case REG_ESAI_TX1:
  774.     case REG_ESAI_TX2:
  775.     case REG_ESAI_TX3:
  776.     case REG_ESAI_TX4:
  777.     case REG_ESAI_TX5:
  778.     case REG_ESAI_RX0:
  779.     case REG_ESAI_RX1:
  780.     case REG_ESAI_RX2:
  781.     case REG_ESAI_RX3:
  782.     case REG_ESAI_SAISR:
  783.         return true;
  784.     default:
  785.         return false;
  786.     }
  787.  
  788. }
  789.  
  790. static bool fsl_esai_writeable_reg(struct device *dev, unsigned int reg)
  791. {
  792.     switch (reg) {
  793.     case REG_ESAI_ETDR:
  794.     case REG_ESAI_ECR:
  795.     case REG_ESAI_TFCR:
  796.     case REG_ESAI_RFCR:
  797.     case REG_ESAI_TX0:
  798.     case REG_ESAI_TX1:
  799.     case REG_ESAI_TX2:
  800.     case REG_ESAI_TX3:
  801.     case REG_ESAI_TX4:
  802.     case REG_ESAI_TX5:
  803.     case REG_ESAI_TSR:
  804.     case REG_ESAI_SAICR:
  805.     case REG_ESAI_TCR:
  806.     case REG_ESAI_TCCR:
  807.     case REG_ESAI_RCR:
  808.     case REG_ESAI_RCCR:
  809.     case REG_ESAI_TSMA:
  810.     case REG_ESAI_TSMB:
  811.     case REG_ESAI_RSMA:
  812.     case REG_ESAI_RSMB:
  813.     case REG_ESAI_PRRC:
  814.     case REG_ESAI_PCRC:
  815.         return true;
  816.     default:
  817.         return false;
  818.     }
  819. }
  820.  
  821. static const struct regmap_config fsl_esai_regmap_config = {
  822.     .reg_bits = 32,
  823.     .reg_stride = 4,
  824.     .val_bits = 32,
  825.  
  826.     .max_register = REG_ESAI_PCRC,
  827.     .readable_reg = fsl_esai_readable_reg,
  828.     .volatile_reg = fsl_esai_volatile_reg,
  829.     .writeable_reg = fsl_esai_writeable_reg,
  830.     .cache_type = REGCACHE_RBTREE,
  831. };
  832.  
  833. static bool fsl_esai_check_xrun(struct snd_pcm_substream *substream)
  834. {
  835.     struct snd_soc_pcm_runtime *rtd = substream->private_data;
  836.     struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  837.     struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(cpu_dai);
  838.     u32 saisr,esr;
  839.     bool returned = 0;
  840.  
  841.     regmap_read(esai_priv->regmap, REG_ESAI_SAISR, &saisr);
  842.     regmap_read(esai_priv->regmap, REG_ESAI_ESR, &esr);
  843.     returned = saisr & (ESAI_SAISR_TUE | ESAI_SAISR_ROE) ;
  844.     //printk(KERN_ERR"XRUN SAISR:0x%08X ESR:0x%08X\n",saisr,esr);
  845.     if(returned)
  846.         printk("Kernel xrun problem\n");
  847.     return returned;
  848. }
  849.  
  850. static int stop_lock_stream(struct snd_pcm_substream *substream)
  851. {
  852.     if (substream) {
  853.         snd_pcm_stream_lock_irq(substream);
  854.         if (substream->runtime->status->state == SNDRV_PCM_STATE_RUNNING)
  855.             substream->ops->trigger(substream, SNDRV_PCM_TRIGGER_STOP);
  856.     }
  857.     return 0;
  858. }
  859.  
  860. static int start_unlock_stream(struct snd_pcm_substream *substream)
  861. {
  862.     if (substream) {
  863.         if (substream->runtime->status->state == SNDRV_PCM_STATE_RUNNING)
  864.             substream->ops->trigger(substream, SNDRV_PCM_TRIGGER_START);
  865.         snd_pcm_stream_unlock_irq(substream);
  866.     }
  867.     return 0;
  868. }
  869.  
  870. /*
  871.  *Here is ESAI underrun reset step:
  872.  *1. Read "TUE" and got TUE=1
  873.  *2. stop DMA.
  874.  *3. stop ESAI TX section.
  875.  *4. Set the transmitter section individual reset "TPR=1"
  876.  *5. Reset the ESAI Transmit FIFO (set ESAI_TFCR[1]=1).
  877.  *6. Config the control registers ESAI_TCCR and ESAI_TCR.config the Transmit FIFO register.
  878.  *7. clear "TPR"
  879.  *8. read "TUE"
  880.  *9. Prefill ESAI TX FIFO.
  881.  *10.Start DMA.
  882.  *11 Enable the ESAI
  883.  */
  884. static void fsl_esai_reset(struct snd_pcm_substream *substream, bool stop)
  885. {
  886.     struct snd_soc_pcm_runtime *rtd = substream->private_data;
  887.     struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  888.     struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(cpu_dai);
  889.     u32 saisr;
  890.  
  891.     printk(KERN_ERR"!!!!!!!! %s(%d) FSL RESET !!!\n",__func__,__LINE__);
  892.     if (stop) {
  893.         stop_lock_stream(esai_priv->substream[0]);
  894.         stop_lock_stream(esai_priv->substream[1]);
  895.     }
  896.  
  897.  
  898.     regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,
  899.                 ESAI_ECR_ESAIEN_MASK | ESAI_ECR_ERST_MASK,
  900.                 ESAI_ECR_ESAIEN | ESAI_ECR_ERST);
  901.     regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,
  902.                 ESAI_ECR_ESAIEN_MASK | ESAI_ECR_ERST_MASK,
  903.                 ESAI_ECR_ESAIEN);
  904.  
  905.     regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, ESAI_xCR_xPR_MASK, ESAI_xCR_xPR);
  906.     regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, ESAI_xCR_xPR_MASK, ESAI_xCR_xPR);
  907.  
  908.     regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC, ESAI_PRRC_PDC_MASK, 0);
  909.     regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC, ESAI_PCRC_PC_MASK, 0);
  910.  
  911.     /*
  912.      * Add fifo reset here, because the regcache_sync will write one more data to ETDR.
  913.      * Which will cause channel shift.
  914.      */
  915.     regmap_update_bits(esai_priv->regmap, REG_ESAI_TFCR, ESAI_xFCR_xFR_MASK, ESAI_xFCR_xFR);
  916.     regmap_update_bits(esai_priv->regmap, REG_ESAI_RFCR, ESAI_xFCR_xFR_MASK, ESAI_xFCR_xFR);
  917.  
  918.     regcache_mark_dirty(esai_priv->regmap);
  919.     regcache_sync(esai_priv->regmap);
  920.  
  921.     regmap_update_bits(esai_priv->regmap, REG_ESAI_TFCR, ESAI_xFCR_xFR_MASK, 0);
  922.     regmap_update_bits(esai_priv->regmap, REG_ESAI_RFCR, ESAI_xFCR_xFR_MASK, 0);
  923.  
  924.     regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, ESAI_xCR_xPR_MASK, 0);
  925.     regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, ESAI_xCR_xPR_MASK, 0);
  926.  
  927.     regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,
  928.                    ESAI_PRRC_PDC_MASK, ESAI_PRRC_PDC(ESAI_GPIO));
  929.     regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,
  930.                    ESAI_PCRC_PC_MASK, ESAI_PCRC_PC(ESAI_GPIO));
  931.  
  932.     regmap_read(esai_priv->regmap, REG_ESAI_SAISR, &saisr);
  933.  
  934.     if (stop) {
  935.         start_unlock_stream(esai_priv->substream[1]);
  936.         start_unlock_stream(esai_priv->substream[0]);
  937.     }
  938. }
  939.  
  940. static int fsl_esai_probe(struct platform_device *pdev)
  941. {
  942.     struct device_node *np = pdev->dev.of_node;
  943.     struct fsl_esai *esai_priv;
  944.     struct resource *res;
  945.     const uint32_t *iprop;
  946.     void __iomem *regs;
  947.     int irq, ret;
  948.     u32 dma_events[2];
  949.  
  950.     esai_priv = devm_kzalloc(&pdev->dev, sizeof(*esai_priv), GFP_KERNEL);
  951.     if (!esai_priv)
  952.         return -ENOMEM;
  953.  
  954.     esai_priv->pdev = pdev;
  955.     strcpy(esai_priv->name, np->name);
  956.  
  957.     /* Get the addresses and IRQ */
  958.     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  959.     regs = devm_ioremap_resource(&pdev->dev, res);
  960.     if (IS_ERR(regs))
  961.         return PTR_ERR(regs);
  962.  
  963.     esai_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
  964.             "core", regs, &fsl_esai_regmap_config);
  965.     if (IS_ERR(esai_priv->regmap)) {
  966.         dev_err(&pdev->dev, "failed to init regmap: %ld\n",
  967.                 PTR_ERR(esai_priv->regmap));
  968.         return PTR_ERR(esai_priv->regmap);
  969.     }
  970.  
  971.     esai_priv->coreclk = devm_clk_get(&pdev->dev, "core");
  972.     if (IS_ERR(esai_priv->coreclk)) {
  973.         dev_err(&pdev->dev, "failed to get core clock: %ld\n",
  974.                 PTR_ERR(esai_priv->coreclk));
  975.         return PTR_ERR(esai_priv->coreclk);
  976.     }
  977.  
  978.     esai_priv->extalclk = devm_clk_get(&pdev->dev, "extal");
  979.     if (IS_ERR(esai_priv->extalclk))
  980.         dev_warn(&pdev->dev, "failed to get extal clock: %ld\n",
  981.                 PTR_ERR(esai_priv->extalclk));
  982.  
  983.     esai_priv->fsysclk = devm_clk_get(&pdev->dev, "fsys");
  984.     if (IS_ERR(esai_priv->fsysclk))
  985.         dev_warn(&pdev->dev, "failed to get fsys clock: %ld\n",
  986.                 PTR_ERR(esai_priv->fsysclk));
  987.  
  988.     esai_priv->dmaclk = devm_clk_get(&pdev->dev, "dma");
  989.     if (IS_ERR(esai_priv->dmaclk)) {
  990.         dev_err(&pdev->dev, "Cannot get dma clock: %ld\n",
  991.                 PTR_ERR(esai_priv->dmaclk));
  992.         return PTR_ERR(esai_priv->dmaclk);
  993.     }
  994.  
  995.     irq = platform_get_irq(pdev, 0);
  996.     if (irq < 0) {
  997.         dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
  998.         return irq;
  999.     }
  1000.  
  1001.     ret = devm_request_irq(&pdev->dev, irq, esai_isr, 0,
  1002.                    esai_priv->name, esai_priv);
  1003.     if (ret) {
  1004.         dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
  1005.         return ret;
  1006.     }
  1007.  
  1008.     /* Set a default slot size */
  1009.     esai_priv->slot_width = 32;
  1010.  
  1011.     /* Set a default master/slave state */
  1012.     esai_priv->slave_mode = true;
  1013.  
  1014.     /* Determine the FIFO depth */
  1015.     iprop = of_get_property(np, "fsl,fifo-depth", NULL);
  1016.     if (iprop)
  1017.         esai_priv->fifo_depth = be32_to_cpup(iprop);
  1018.     else
  1019.         esai_priv->fifo_depth = 64;
  1020.  
  1021.     esai_priv->dma_params_tx.maxburst = 64;
  1022.     esai_priv->dma_params_rx.maxburst = 64;
  1023.     esai_priv->dma_params_tx.addr = res->start + REG_ESAI_ETDR;
  1024.     esai_priv->dma_params_rx.addr = res->start + REG_ESAI_ERDR;
  1025.  
  1026.     esai_priv->dma_params_tx.filter_data = &esai_priv->filter_data_tx;
  1027.     esai_priv->dma_params_rx.filter_data = &esai_priv->filter_data_rx;
  1028.  
  1029.     ret = of_property_read_u32_array(pdev->dev.of_node,
  1030.                     "fsl,esai-dma-events", dma_events, 2);
  1031.     if (ret) {
  1032.         dev_err(&pdev->dev, "could not get dma events\n");
  1033.         return ret;
  1034.     }
  1035.  
  1036.     esai_priv->filter_data_tx.dma_request0 = dma_events[0];
  1037.     esai_priv->filter_data_rx.dma_request0 = dma_events[1];
  1038.     esai_priv->filter_data_tx.peripheral_type = IMX_DMATYPE_ESAI;
  1039.     esai_priv->filter_data_rx.peripheral_type = IMX_DMATYPE_ESAI;
  1040.  
  1041.     esai_priv->dma_params_tx.check_xrun = fsl_esai_check_xrun;
  1042.     esai_priv->dma_params_rx.check_xrun = fsl_esai_check_xrun;
  1043.     esai_priv->dma_params_tx.device_reset = fsl_esai_reset;
  1044.     esai_priv->dma_params_rx.device_reset = fsl_esai_reset;
  1045.  
  1046.     esai_priv->synchronous =
  1047.         of_property_read_bool(np, "fsl,esai-synchronous");
  1048.  
  1049.     /* Implement full symmetry for synchronous mode */
  1050.     if (esai_priv->synchronous) {
  1051.         printk(KERN_ERR"Using ESAI in Synchronous mode\n");
  1052.         fsl_esai_dai.symmetric_rates = 1;
  1053.         fsl_esai_dai.symmetric_channels = 1;
  1054.         fsl_esai_dai.symmetric_samplebits = 1;
  1055.     }
  1056.  
  1057.     dev_set_drvdata(&pdev->dev, esai_priv);
  1058.  
  1059.     /* Reset ESAI unit */
  1060.     ret = regmap_write(esai_priv->regmap, REG_ESAI_ECR, ESAI_ECR_ERST);
  1061.     if (ret) {
  1062.         dev_err(&pdev->dev, "failed to reset ESAI: %d\n", ret);
  1063.         return ret;
  1064.     }
  1065.  
  1066.     /*
  1067.      * We need to enable ESAI so as to access some of its registers.
  1068.      * Otherwise, we would fail to dump regmap from user space.
  1069.      */
  1070.     ret = regmap_write(esai_priv->regmap, REG_ESAI_ECR, ESAI_ECR_ESAIEN);
  1071.     if (ret) {
  1072.         dev_err(&pdev->dev, "failed to enable ESAI: %d\n", ret);
  1073.         return ret;
  1074.     }
  1075.  
  1076.     ret = devm_snd_soc_register_component(&pdev->dev, &fsl_esai_component,
  1077.                           &fsl_esai_dai, 1);
  1078.     if (ret) {
  1079.         dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
  1080.         return ret;
  1081.     }
  1082.  
  1083.     ret = imx_pcm_dma_init(pdev, SND_DMAENGINE_PCM_FLAG_NO_RESIDUE |
  1084.                     SND_DMAENGINE_PCM_FLAG_NO_DT |
  1085.                     SND_DMAENGINE_PCM_FLAG_COMPAT,
  1086.                     IMX_ESAI_DMABUF_SIZE);
  1087.     if (ret)
  1088.         dev_err(&pdev->dev, "failed to init imx pcm dma: %d\n", ret);
  1089.  
  1090.     return ret;
  1091. }
  1092.  
  1093. static const struct of_device_id fsl_esai_dt_ids[] = {
  1094.     { .compatible = "fsl,imx35-esai", },
  1095.     {}
  1096. };
  1097. MODULE_DEVICE_TABLE(of, fsl_esai_dt_ids);
  1098.  
  1099. #if CONFIG_PM_SLEEP
  1100. static int fsl_esai_suspend(struct device *dev)
  1101. {
  1102.     struct fsl_esai *esai = dev_get_drvdata(dev);
  1103.  
  1104.     regcache_cache_only(esai->regmap, true);
  1105.     regcache_mark_dirty(esai->regmap);
  1106.  
  1107.     return 0;
  1108. }
  1109.  
  1110. static int fsl_esai_resume(struct device *dev)
  1111. {
  1112.     struct fsl_esai *esai = dev_get_drvdata(dev);
  1113.     int ret;
  1114.  
  1115.     regcache_cache_only(esai->regmap, false);
  1116.  
  1117.     /* FIFO reset for safety */
  1118.     regmap_update_bits(esai->regmap, REG_ESAI_TFCR,
  1119.                ESAI_xFCR_xFR, ESAI_xFCR_xFR);
  1120.     regmap_update_bits(esai->regmap, REG_ESAI_RFCR,
  1121.                ESAI_xFCR_xFR, ESAI_xFCR_xFR);
  1122.  
  1123.     ret = regcache_sync(esai->regmap);
  1124.     if (ret)
  1125.         return ret;
  1126.  
  1127.     /* FIFO reset done */
  1128.     regmap_update_bits(esai->regmap, REG_ESAI_TFCR, ESAI_xFCR_xFR, 0);
  1129.     regmap_update_bits(esai->regmap, REG_ESAI_RFCR, ESAI_xFCR_xFR, 0);
  1130.  
  1131.     return 0;
  1132. }
  1133. #endif /* CONFIG_PM_SLEEP */
  1134.  
  1135. static const struct dev_pm_ops fsl_esai_pm_ops = {
  1136.     SET_SYSTEM_SLEEP_PM_OPS(fsl_esai_suspend, fsl_esai_resume)
  1137. };
  1138.  
  1139. static struct platform_driver fsl_esai_driver = {
  1140.     .probe = fsl_esai_probe,
  1141.     .driver = {
  1142.         .name = "fsl-esai-dai",
  1143.         .owner = THIS_MODULE,
  1144.         .pm = &fsl_esai_pm_ops,
  1145.         .of_match_table = fsl_esai_dt_ids,
  1146.     },
  1147. };
  1148.  
  1149. module_platform_driver(fsl_esai_driver);
  1150.  
  1151. MODULE_AUTHOR("Freescale Semiconductor, Inc.");
  1152. MODULE_DESCRIPTION("Freescale ESAI CPU DAI driver");
  1153. MODULE_LICENSE("GPL v2");
  1154. MODULE_ALIAS("platform:fsl-esai-dai");
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