This week only. Pastebin PRO Accounts Christmas Special! Don't miss out!Want more features on Pastebin? Sign Up, it's FREE!
Guest

Coreboot_Ultra40M2

By: a guest on Oct 31st, 2011  |  syntax: None  |  size: 5.42 KB  |  views: 41  |  expires: Never
download  |  raw  |  embed  |  report abuse  |  print
Text below is selected. Please press Ctrl+C to copy to your clipboard. (⌘+C on Mac)
  1. coreboot-4.0-1815-gb9da3cd-dirty Fri Oct 28 13:26:09 PDT 2011 starting...
  2. *sysinfo range: [000cf000,000cf730]
  3. bsp_apicid=00
  4. Enabling routing table for node 00 done.
  5. Enabling SMP settings
  6. (0,1) link=00
  7. (1,0) link=02
  8. setup_remote_node: done
  9. Renaming current temporary node to 01 done.
  10. Enabling routing table for node 01 done.
  11. 02 nodes initialized.
  12. coherent_ht_finalize
  13. done
  14. core0 started:  01
  15. started ap apicid: * AP 01started
  16. * AP 03started
  17.  
  18. SBLink=01
  19. NC node|link=01
  20. NC node|link=02
  21.     busn=40
  22. entering optimize_link_incoherent_ht
  23. sysinfo->link_pair_num=0x2
  24. entering ht_optimize_link
  25. pos=0xaa, unfiltered freq_cap=0x8075
  26. pos=0xaa, filtered freq_cap=0x75
  27. pos=0x52, unfiltered freq_cap=0x7f
  28. pos=0x52, filtered freq_cap=0x7f
  29. freq_cap1=0x75, freq_cap2=0x7f
  30. dev1 old_freq=0x6, freq=0x6, needs_reset=0x0
  31. dev2 old_freq=0x6, freq=0x6, needs_reset=0x0
  32. width_cap1=0x11, width_cap2=0x11
  33. dev1 input ln_width1=0x4, ln_width2=0x4
  34. dev1 input width=0x1
  35. dev1 output ln_width1=0x4, ln_width2=0x4
  36. dev1 input|output width=0x11
  37. old dev1 input|output width=0x11
  38. dev2 input|output width=0x11
  39. old dev2 input|output width=0x11
  40. after ht_optimize_link for link pair 0, reset_needed=0x0
  41. entering ht_optimize_link
  42. pos=0xca, unfiltered freq_cap=0x8075
  43. pos=0xca, filtered freq_cap=0x75
  44. pos=0x52, unfiltered freq_cap=0x7f
  45. pos=0x52, filtered freq_cap=0x7f
  46. freq_cap1=0x75, freq_cap2=0x7f
  47. dev1 old_freq=0x6, freq=0x6, needs_reset=0x0
  48. dev2 old_freq=0x6, freq=0x6, needs_reset=0x0
  49. width_cap1=0x11, width_cap2=0x11
  50. dev1 input ln_width1=0x4, ln_width2=0x4
  51. dev1 input width=0x1
  52. dev1 output ln_width1=0x4, ln_width2=0x4
  53. dev1 input|output width=0x11
  54. old dev1 input|output width=0x11
  55. dev2 input|output width=0x11
  56. old dev2 input|output width=0x11
  57. after ht_optimize_link for link pair 1, reset_needed=0x0
  58. after optimize_link_read_pointers_chain, reset_needed=0x0
  59. mcp55_num:01
  60. ht reset -
  61.  
  62. coreboot-4.0-1815-gb9da3cd-dirty Fri Oct 28 13:26:09 PDT 2011 starting...
  63. *sysinfo range: [000cf000,000cf730]
  64. bsp_apicid=00
  65. Enabling routing table for node 00 done.
  66. Enabling SMP settings
  67. (0,1) link=00
  68. (1,0) link=02
  69. setup_remote_node: done
  70. Renaming current temporary node to 01 done.
  71. Enabling routing table for node 01 done.
  72. 02 nodes initialized.
  73. coherent_ht_finalize
  74. done
  75. core0 started:  01
  76. started ap apicid: * AP 01started
  77. * AP 03started
  78.  
  79. SBLink=01
  80. NC node|link=01
  81. NC node|link=02
  82.     busn=40
  83. entering optimize_link_incoherent_ht
  84. sysinfo->link_pair_num=0x2
  85. entering ht_optimize_link
  86. pos=0xaa, unfiltered freq_cap=0x8075
  87. pos=0xaa, filtered freq_cap=0x75
  88. pos=0x52, unfiltered freq_cap=0x7f
  89. pos=0x52, filtered freq_cap=0x7f
  90. freq_cap1=0x75, freq_cap2=0x7f
  91. dev1 old_freq=0x6, freq=0x6, needs_reset=0x0
  92. dev2 old_freq=0x6, freq=0x6, needs_reset=0x0
  93. width_cap1=0x11, width_cap2=0x11
  94. dev1 input ln_width1=0x4, ln_width2=0x4
  95. dev1 input width=0x1
  96. dev1 output ln_width1=0x4, ln_width2=0x4
  97. dev1 input|output width=0x11
  98. old dev1 input|output width=0x11
  99. dev2 input|output width=0x11
  100. old dev2 input|output width=0x11
  101. after ht_optimize_link for link pair 0, reset_needed=0x0
  102. entering ht_optimize_link
  103. pos=0xca, unfiltered freq_cap=0x8075
  104. pos=0xca, filtered freq_cap=0x75
  105. pos=0x52, unfiltered freq_cap=0x7f
  106. pos=0x52, filtered freq_cap=0x7f
  107. freq_cap1=0x75, freq_cap2=0x7f
  108. dev1 old_freq=0x6, freq=0x6, needs_reset=0x0
  109. dev2 old_freq=0x6, freq=0x6, needs_reset=0x0
  110. width_cap1=0x11, width_cap2=0x11
  111. dev1 input ln_width1=0x4, ln_width2=0x4
  112. dev1 input width=0x1
  113. dev1 output ln_width1=0x4, ln_width2=0x4
  114. dev1 input|output width=0x11
  115. old dev1 input|output width=0x11
  116. dev2 input|output width=0x11
  117. old dev2 input|output width=0x11
  118. after ht_optimize_link for link pair 1, reset_needed=0x0
  119. after optimize_link_read_pointers_chain, reset_needed=0x0
  120. mcp55_num:01
  121. Ram1.00
  122. setting up CPU 00 northbridge registers
  123. done.
  124. Ram1.01
  125. setting up CPU 01 northbridge registers
  126. done.
  127. Ram2.00
  128. sdram_set_spd_registers: paramx :000cef28
  129. Enabling dual channel memory
  130. Registered
  131. 333MHz
  132. 333MHz
  133. Interleaved
  134. RAM end at 0x00400000 kB
  135. Ram2.01
  136. sdram_set_spd_registers: paramx :000cef28
  137. Enabling dual channel memory
  138. Registered
  139. 333MHz
  140. 333MHz
  141. Interleaved
  142. RAM end at 0x00800000 kB
  143. Ram3
  144. ECC enabled
  145. ECC enabled
  146. Initializing memory:  done
  147. Initializing memory:  done
  148. RAM end at 0x00900000 kB
  149. set DQS timing:RcvrEn:Pass1: 00
  150.  done
  151. set DQS timing:DQSPos: 00
  152. TrainDQSRdWrPos: buf_a:000ce9a0
  153. TrainDQSPos: MutualCSPassW[48] :000ce878
  154. TrainDQSPos: MutualCSPassW[48] :000ce878
  155. TrainDQSPos: MutualCSPassW[48] :000ce878
  156. TrainDQSPos: MutualCSPassW[48] :000ce878
  157. TrainDQSPos: MutualCSPassW[48] :000ce878
  158. TrainDQSPos: MutualCSPassW[48] :000ce878
  159.  
  160. TrainDQSPos: MutualCSPassW[48] :000ce888
  161.  
  162. TrainDQSPos: MutualCSPassW[48] :000ce878
  163. TrainDQSPos: MutualCSPassW[48] :000ce878
  164. TrainDQSPos: MutualCSPassW[48] :000ce878
  165. TrainDQSPos: MutualCSPassW[48] :000ce878
  166. TrainDQSPos: MutualCSPassW[48] :000ce878
  167. TrainDQSPos: MutualCSPassW[48] :000ce878
  168.  
  169. TrainDQSPos: MutualCSPassW[48] :000ce888
  170.  done
  171. set DQS timing:RcvrEn:Pass2: 00
  172.  done
  173. Total DQS Training : tsc [00]=0000000552e53b8f
  174. Total DQS Training : tsc [01]=00000005bbc4d07e
  175. Total DQS Training : tsc [02]=0000006b02b708c6
  176. Total DQS Training : tsc [03]=0000006b93194cab
  177. Ram4
  178. v_esp=000cef68
  179. testx = 5a5a5a5a
  180. Copying data from cache to RAM -- switching to use RAM as stack... Done
  181. testx = 5a5a5a5a
  182. Disabling cache as ram now
  183. Clearing initial memory region: Done
  184.  
  185.  
  186.  
  187. INIT detected from  --- { APICID = 00 NODEID = 00 COREID = 00} ---
  188.  
  189. Issuing SOFT_RESET...
  190.  
clone this paste RAW Paste Data