API tools faq
paste
Advertisement
Guest User

cpmac.c file for AR7 devices OpenWRT

a guest
Feb 2nd, 2014
136
0
Never
Add comment
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
text 36.61 KB | None | 0 0
raw download clone embed print report
  1. /*
  2. * Copyright (C) 2006, 2007 Eugene Konev
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; either version 2 of the License, or
  7. * (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  17. */
  18.  
  19. #include <linux/module.h>
  20. #include <linux/init.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/moduleparam.h>
  23.  
  24. #include <linux/sched.h>
  25. #include <linux/kernel.h>
  26. #include <linux/slab.h>
  27. #include <linux/errno.h>
  28. #include <linux/types.h>
  29. #include <linux/delay.h>
  30.  
  31. #include <linux/netdevice.h>
  32. #include <linux/if_vlan.h>
  33. #include <linux/etherdevice.h>
  34. #include <linux/ethtool.h>
  35. #include <linux/skbuff.h>
  36. #include <linux/mii.h>
  37. #include <linux/phy.h>
  38. #include <linux/platform_device.h>
  39. #include <linux/dma-mapping.h>
  40. #include <linux/clk.h>
  41. #include <linux/gpio.h>
  42. #include <linux/atomic.h>
  43.  
  44. MODULE_AUTHOR("Eugene Konev <ejka@imfi.kspu.ru>");
  45. MODULE_DESCRIPTION("TI AR7 ethernet driver (CPMAC)");
  46. MODULE_LICENSE("GPL");
  47. MODULE_ALIAS("platform:cpmac");
  48.  
  49. static int debug_level = 8;
  50.  
  51. /* Next is only used in cpmac_probe, so it's pointless to change them */
  52. module_param(debug_level, int, 0444);
  53.  
  54. MODULE_PARM_DESC(debug_level, "Number of NETIF_MSG bits to enable");
  55.  
  56. #define CPMAC_VERSION "0.5.2"
  57. /* frame size + 802.1q tag + FCS size */
  58. #define CPMAC_SKB_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
  59. #define CPMAC_QUEUES 8
  60.  
  61. /* Ethernet registers */
  62. #define CPMAC_TX_CONTROL 0x0004
  63. #define CPMAC_TX_TEARDOWN 0x0008
  64. #define CPMAC_RX_CONTROL 0x0014
  65. #define CPMAC_RX_TEARDOWN 0x0018
  66. #define CPMAC_MBP 0x0100
  67. # define MBP_RXPASSCRC 0x40000000
  68. # define MBP_RXQOS 0x20000000
  69. # define MBP_RXNOCHAIN 0x10000000
  70. # define MBP_RXCMF 0x01000000
  71. # define MBP_RXSHORT 0x00800000
  72. # define MBP_RXCEF 0x00400000
  73. # define MBP_RXPROMISC 0x00200000
  74. # define MBP_PROMISCCHAN(channel) (((channel) & 0x7) << 16)
  75. # define MBP_RXBCAST 0x00002000
  76. # define MBP_BCASTCHAN(channel) (((channel) & 0x7) << 8)
  77. # define MBP_RXMCAST 0x00000020
  78. # define MBP_MCASTCHAN(channel) ((channel) & 0x7)
  79. #define CPMAC_UNICAST_ENABLE 0x0104
  80. #define CPMAC_UNICAST_CLEAR 0x0108
  81. #define CPMAC_MAX_LENGTH 0x010c
  82. #define CPMAC_BUFFER_OFFSET 0x0110
  83. #define CPMAC_MAC_CONTROL 0x0160
  84. # define MAC_TXPTYPE 0x00000200
  85. # define MAC_TXPACE 0x00000040
  86. # define MAC_MII 0x00000020
  87. # define MAC_TXFLOW 0x00000010
  88. # define MAC_RXFLOW 0x00000008
  89. # define MAC_MTEST 0x00000004
  90. # define MAC_LOOPBACK 0x00000002
  91. # define MAC_FDX 0x00000001
  92. #define CPMAC_MAC_STATUS 0x0164
  93. # define MAC_STATUS_QOS 0x00000004
  94. # define MAC_STATUS_RXFLOW 0x00000002
  95. # define MAC_STATUS_TXFLOW 0x00000001
  96. #define CPMAC_TX_INT_ENABLE 0x0178
  97. #define CPMAC_TX_INT_CLEAR 0x017c
  98. #define CPMAC_MAC_INT_VECTOR 0x0180
  99. # define MAC_INT_STATUS 0x00080000
  100. # define MAC_INT_HOST 0x00040000
  101. # define MAC_INT_RX 0x00020000
  102. # define MAC_INT_TX 0x00010000
  103. #define CPMAC_MAC_EOI_VECTOR 0x0184
  104. #define CPMAC_RX_INT_ENABLE 0x0198
  105. #define CPMAC_RX_INT_CLEAR 0x019c
  106. #define CPMAC_MAC_INT_ENABLE 0x01a8
  107. #define CPMAC_MAC_INT_CLEAR 0x01ac
  108. #define CPMAC_MAC_ADDR_LO(channel) (0x01b0 + (channel) * 4)
  109. #define CPMAC_MAC_ADDR_MID 0x01d0
  110. #define CPMAC_MAC_ADDR_HI 0x01d4
  111. #define CPMAC_MAC_HASH_LO 0x01d8
  112. #define CPMAC_MAC_HASH_HI 0x01dc
  113. #define CPMAC_TX_PTR(channel) (0x0600 + (channel) * 4)
  114. #define CPMAC_RX_PTR(channel) (0x0620 + (channel) * 4)
  115. #define CPMAC_TX_ACK(channel) (0x0640 + (channel) * 4)
  116. #define CPMAC_RX_ACK(channel) (0x0660 + (channel) * 4)
  117. #define CPMAC_REG_END 0x0680
  118. /*
  119. * Rx/Tx statistics
  120. * TODO: use some of them to fill stats in cpmac_stats()
  121. */
  122. #define CPMAC_STATS_RX_GOOD 0x0200
  123. #define CPMAC_STATS_RX_BCAST 0x0204
  124. #define CPMAC_STATS_RX_MCAST 0x0208
  125. #define CPMAC_STATS_RX_PAUSE 0x020c
  126. #define CPMAC_STATS_RX_CRC 0x0210
  127. #define CPMAC_STATS_RX_ALIGN 0x0214
  128. #define CPMAC_STATS_RX_OVER 0x0218
  129. #define CPMAC_STATS_RX_JABBER 0x021c
  130. #define CPMAC_STATS_RX_UNDER 0x0220
  131. #define CPMAC_STATS_RX_FRAG 0x0224
  132. #define CPMAC_STATS_RX_FILTER 0x0228
  133. #define CPMAC_STATS_RX_QOSFILTER 0x022c
  134. #define CPMAC_STATS_RX_OCTETS 0x0230
  135.  
  136. #define CPMAC_STATS_TX_GOOD 0x0234
  137. #define CPMAC_STATS_TX_BCAST 0x0238
  138. #define CPMAC_STATS_TX_MCAST 0x023c
  139. #define CPMAC_STATS_TX_PAUSE 0x0240
  140. #define CPMAC_STATS_TX_DEFER 0x0244
  141. #define CPMAC_STATS_TX_COLLISION 0x0248
  142. #define CPMAC_STATS_TX_SINGLECOLL 0x024c
  143. #define CPMAC_STATS_TX_MULTICOLL 0x0250
  144. #define CPMAC_STATS_TX_EXCESSCOLL 0x0254
  145. #define CPMAC_STATS_TX_LATECOLL 0x0258
  146. #define CPMAC_STATS_TX_UNDERRUN 0x025c
  147. #define CPMAC_STATS_TX_CARRIERSENSE 0x0260
  148. #define CPMAC_STATS_TX_OCTETS 0x0264
  149.  
  150. #define cpmac_read(base, reg) (readl((void __iomem *)(base) + (reg)))
  151. #define cpmac_write(base, reg, val) (writel(val, (void __iomem *)(base) + \
  152. (reg)))
  153.  
  154. /* MDIO bus */
  155. #define CPMAC_MDIO_VERSION 0x0000
  156. #define CPMAC_MDIO_CONTROL 0x0004
  157. # define MDIOC_IDLE 0x80000000
  158. # define MDIOC_ENABLE 0x40000000
  159. # define MDIOC_PREAMBLE 0x00100000
  160. # define MDIOC_FAULT 0x00080000
  161. # define MDIOC_FAULTDETECT 0x00040000
  162. # define MDIOC_INTTEST 0x00020000
  163. # define MDIOC_CLKDIV(div) ((div) & 0xff)
  164. #define CPMAC_MDIO_ALIVE 0x0008
  165. #define CPMAC_MDIO_LINK 0x000c
  166. #define CPMAC_MDIO_ACCESS(channel) (0x0080 + (channel) * 8)
  167. # define MDIO_BUSY 0x80000000
  168. # define MDIO_WRITE 0x40000000
  169. # define MDIO_REG(reg) (((reg) & 0x1f) << 21)
  170. # define MDIO_PHY(phy) (((phy) & 0x1f) << 16)
  171. # define MDIO_DATA(data) ((data) & 0xffff)
  172. #define CPMAC_MDIO_PHYSEL(channel) (0x0084 + (channel) * 8)
  173. # define PHYSEL_LINKSEL 0x00000040
  174. # define PHYSEL_LINKINT 0x00000020
  175.  
  176. struct cpmac_desc {
  177. u32 hw_next;
  178. u32 hw_data;
  179. u16 buflen;
  180. u16 bufflags;
  181. u16 datalen;
  182. u16 dataflags;
  183. #define CPMAC_SOP 0x8000
  184. #define CPMAC_EOP 0x4000
  185. #define CPMAC_OWN 0x2000
  186. #define CPMAC_EOQ 0x1000
  187. struct sk_buff *skb;
  188. struct cpmac_desc *next;
  189. struct cpmac_desc *prev;
  190. dma_addr_t mapping;
  191. dma_addr_t data_mapping;
  192. };
  193.  
  194. struct cpmac_priv {
  195. spinlock_t lock;
  196. spinlock_t rx_lock;
  197. struct cpmac_desc *rx_head;
  198. int ring_size;
  199. struct cpmac_desc *desc_ring;
  200. dma_addr_t dma_ring;
  201. void __iomem *regs;
  202. struct mii_bus *mii_bus;
  203. struct phy_device *phy;
  204. char phy_name[MII_BUS_ID_SIZE + 3];
  205. int oldlink, oldspeed, oldduplex;
  206. u32 msg_enable;
  207. struct net_device *dev;
  208. struct work_struct reset_work;
  209. struct platform_device *pdev;
  210. struct napi_struct napi;
  211. atomic_t reset_pending;
  212. };
  213.  
  214. static irqreturn_t cpmac_irq(int, void *);
  215. static void cpmac_hw_start(struct net_device *dev);
  216. static void cpmac_hw_stop(struct net_device *dev);
  217. static int cpmac_stop(struct net_device *dev);
  218. static int cpmac_open(struct net_device *dev);
  219.  
  220. static void cpmac_dump_regs(struct net_device *dev)
  221. {
  222. int i;
  223. struct cpmac_priv *priv = netdev_priv(dev);
  224. for (i = 0; i < CPMAC_REG_END; i += 4) {
  225. if (i % 16 == 0) {
  226. if (i)
  227. pr_cont("\n");
  228. printk(KERN_DEBUG "%s: reg[%p]:", dev->name,
  229. priv->regs + i);
  230. }
  231. printk(" %08x", cpmac_read(priv->regs, i));
  232. }
  233. printk("\n");
  234. }
  235.  
  236. static void cpmac_dump_desc(struct net_device *dev, struct cpmac_desc *desc)
  237. {
  238. int i;
  239. printk(KERN_DEBUG "%s: desc[%p]:", dev->name, desc);
  240. for (i = 0; i < sizeof(*desc) / 4; i++)
  241. printk(" %08x", ((u32 *)desc)[i]);
  242. printk("\n");
  243. }
  244.  
  245. static void cpmac_dump_all_desc(struct net_device *dev)
  246. {
  247. struct cpmac_priv *priv = netdev_priv(dev);
  248. struct cpmac_desc *dump = priv->rx_head;
  249. do {
  250. cpmac_dump_desc(dev, dump);
  251. dump = dump->next;
  252. } while (dump != priv->rx_head);
  253. }
  254.  
  255. static void cpmac_dump_skb(struct net_device *dev, struct sk_buff *skb)
  256. {
  257. int i;
  258. printk(KERN_DEBUG "%s: skb 0x%p, len=%d\n", dev->name, skb, skb->len);
  259. for (i = 0; i < skb->len; i++) {
  260. if (i % 16 == 0) {
  261. if (i)
  262. pr_cont("\n");
  263. printk(KERN_DEBUG "%s: data[%p]:", dev->name,
  264. skb->data + i);
  265. }
  266. printk(" %02x", ((u8 *)skb->data)[i]);
  267. }
  268. printk("\n");
  269. }
  270.  
  271. static int cpmac_mdio_read(struct mii_bus *bus, int phy_id, int reg)
  272. {
  273. u32 val;
  274.  
  275. while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
  276. cpu_relax();
  277. cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_REG(reg) |
  278. MDIO_PHY(phy_id));
  279. while ((val = cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0))) & MDIO_BUSY)
  280. cpu_relax();
  281. return MDIO_DATA(val);
  282. }
  283.  
  284. static int cpmac_mdio_write(struct mii_bus *bus, int phy_id,
  285. int reg, u16 val)
  286. {
  287. while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
  288. cpu_relax();
  289. cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_WRITE |
  290. MDIO_REG(reg) | MDIO_PHY(phy_id) | MDIO_DATA(val));
  291. return 0;
  292. }
  293.  
  294. static int cpmac_mdio_reset(struct mii_bus *bus)
  295. {
  296. struct clk *cpmac_clk;
  297.  
  298. cpmac_clk = clk_get(&bus->dev, "cpmac");
  299. if (IS_ERR(cpmac_clk)) {
  300. printk(KERN_ERR "unable to get cpmac clock\n");
  301. return -1;
  302. }
  303. ar7_device_reset(AR7_RESET_BIT_MDIO);
  304. cpmac_write(bus->priv, CPMAC_MDIO_CONTROL, MDIOC_ENABLE |
  305. MDIOC_CLKDIV(clk_get_rate(cpmac_clk) / 2200000 - 1));
  306. return 0;
  307. }
  308.  
  309. static int mii_irqs[PHY_MAX_ADDR] = { PHY_POLL, };
  310.  
  311. static struct mii_bus *cpmac_mii;
  312.  
  313. static int cpmac_config(struct net_device *dev, struct ifmap *map)
  314. {
  315. if (dev->flags & IFF_UP)
  316. return -EBUSY;
  317.  
  318. /* Don't allow changing the I/O address */
  319. if (map->base_addr != dev->base_addr)
  320. return -EOPNOTSUPP;
  321.  
  322. /* ignore other fields */
  323. return 0;
  324. }
  325.  
  326. static void cpmac_set_multicast_list(struct net_device *dev)
  327. {
  328. struct netdev_hw_addr *ha;
  329. u8 tmp;
  330. u32 mbp, bit, hash[2] = { 0, };
  331. struct cpmac_priv *priv = netdev_priv(dev);
  332.  
  333. mbp = cpmac_read(priv->regs, CPMAC_MBP);
  334. if (dev->flags & IFF_PROMISC) {
  335. cpmac_write(priv->regs, CPMAC_MBP, (mbp & ~MBP_PROMISCCHAN(0)) |
  336. MBP_RXPROMISC);
  337. } else {
  338. cpmac_write(priv->regs, CPMAC_MBP, mbp & ~MBP_RXPROMISC);
  339. if (dev->flags & IFF_ALLMULTI) {
  340. /* enable all multicast mode */
  341. cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, 0xffffffff);
  342. cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, 0xffffffff);
  343. } else {
  344. /*
  345. * cpmac uses some strange mac address hashing
  346. * (not crc32)
  347. */
  348. netdev_for_each_mc_addr(ha, dev) {
  349. bit = 0;
  350. tmp = ha->addr[0];
  351. bit ^= (tmp >> 2) ^ (tmp << 4);
  352. tmp = ha->addr[1];
  353. bit ^= (tmp >> 4) ^ (tmp << 2);
  354. tmp = ha->addr[2];
  355. bit ^= (tmp >> 6) ^ tmp;
  356. tmp = ha->addr[3];
  357. bit ^= (tmp >> 2) ^ (tmp << 4);
  358. tmp = ha->addr[4];
  359. bit ^= (tmp >> 4) ^ (tmp << 2);
  360. tmp = ha->addr[5];
  361. bit ^= (tmp >> 6) ^ tmp;
  362. bit &= 0x3f;
  363. hash[bit / 32] |= 1 << (bit % 32);
  364. }
  365.  
  366. cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, hash[0]);
  367. cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, hash[1]);
  368. }
  369. }
  370. }
  371.  
  372. static struct sk_buff *cpmac_rx_one(struct cpmac_priv *priv,
  373. struct cpmac_desc *desc)
  374. {
  375. struct sk_buff *skb, *result = NULL;
  376.  
  377. if (unlikely(netif_msg_hw(priv)))
  378. cpmac_dump_desc(priv->dev, desc);
  379. cpmac_write(priv->regs, CPMAC_RX_ACK(0), (u32)desc->mapping);
  380. if (unlikely(!desc->datalen)) {
  381. if (netif_msg_rx_err(priv) && net_ratelimit())
  382. printk(KERN_WARNING "%s: rx: spurious interrupt\n",
  383. priv->dev->name);
  384. return NULL;
  385. }
  386.  
  387. skb = netdev_alloc_skb_ip_align(priv->dev, CPMAC_SKB_SIZE);
  388. if (likely(skb)) {
  389. skb_put(desc->skb, desc->datalen);
  390. desc->skb->protocol = eth_type_trans(desc->skb, priv->dev);
  391. skb_checksum_none_assert(desc->skb);
  392. priv->dev->stats.rx_packets++;
  393. priv->dev->stats.rx_bytes += desc->datalen;
  394. result = desc->skb;
  395. dma_unmap_single(&priv->dev->dev, desc->data_mapping,
  396. CPMAC_SKB_SIZE, DMA_FROM_DEVICE);
  397. desc->skb = skb;
  398. desc->data_mapping = dma_map_single(&priv->dev->dev, skb->data,
  399. CPMAC_SKB_SIZE,
  400. DMA_FROM_DEVICE);
  401. desc->hw_data = (u32)desc->data_mapping;
  402. if (unlikely(netif_msg_pktdata(priv))) {
  403. printk(KERN_DEBUG "%s: received packet:\n",
  404. priv->dev->name);
  405. cpmac_dump_skb(priv->dev, result);
  406. }
  407. } else {
  408. if (netif_msg_rx_err(priv) && net_ratelimit())
  409. printk(KERN_WARNING
  410. "%s: low on skbs, dropping packet\n",
  411. priv->dev->name);
  412. priv->dev->stats.rx_dropped++;
  413. }
  414.  
  415. desc->buflen = CPMAC_SKB_SIZE;
  416. desc->dataflags = CPMAC_OWN;
  417.  
  418. return result;
  419. }
  420.  
  421. static int cpmac_poll(struct napi_struct *napi, int budget)
  422. {
  423. struct sk_buff *skb;
  424. struct cpmac_desc *desc, *restart;
  425. struct cpmac_priv *priv = container_of(napi, struct cpmac_priv, napi);
  426. int received = 0, processed = 0;
  427.  
  428. spin_lock(&priv->rx_lock);
  429. if (unlikely(!priv->rx_head)) {
  430. if (netif_msg_rx_err(priv) && net_ratelimit())
  431. printk(KERN_WARNING "%s: rx: polling, but no queue\n",
  432. priv->dev->name);
  433. spin_unlock(&priv->rx_lock);
  434. napi_complete(napi);
  435. return 0;
  436. }
  437.  
  438. desc = priv->rx_head;
  439. restart = NULL;
  440. while (((desc->dataflags & CPMAC_OWN) == 0) && (received < budget)) {
  441. processed++;
  442.  
  443. if ((desc->dataflags & CPMAC_EOQ) != 0) {
  444. /* The last update to eoq->hw_next didn't happen
  445. * soon enough, and the receiver stopped here.
  446. *Remember this descriptor so we can restart
  447. * the receiver after freeing some space.
  448. */
  449. if (unlikely(restart)) {
  450. if (netif_msg_rx_err(priv))
  451. printk(KERN_ERR "%s: poll found a"
  452. " duplicate EOQ: %p and %p\n",
  453. priv->dev->name, restart, desc);
  454. goto fatal_error;
  455. }
  456.  
  457. restart = desc->next;
  458. }
  459.  
  460. skb = cpmac_rx_one(priv, desc);
  461. if (likely(skb)) {
  462. netif_receive_skb(skb);
  463. received++;
  464. }
  465. desc = desc->next;
  466. }
  467.  
  468. if (desc != priv->rx_head) {
  469. /* We freed some buffers, but not the whole ring,
  470. * add what we did free to the rx list */
  471. desc->prev->hw_next = (u32)0;
  472. priv->rx_head->prev->hw_next = priv->rx_head->mapping;
  473. }
  474.  
  475. /* Optimization: If we did not actually process an EOQ (perhaps because
  476. * of quota limits), check to see if the tail of the queue has EOQ set.
  477. * We should immediately restart in that case so that the receiver can
  478. * restart and run in parallel with more packet processing.
  479. * This lets us handle slightly larger bursts before running
  480. * out of ring space (assuming dev->weight < ring_size) */
  481.  
  482. if (!restart &&
  483. (priv->rx_head->prev->dataflags & (CPMAC_OWN|CPMAC_EOQ))
  484. == CPMAC_EOQ &&
  485. (priv->rx_head->dataflags & CPMAC_OWN) != 0) {
  486. /* reset EOQ so the poll loop (above) doesn't try to
  487. * restart this when it eventually gets to this descriptor.
  488. */
  489. priv->rx_head->prev->dataflags &= ~CPMAC_EOQ;
  490. restart = priv->rx_head;
  491. }
  492.  
  493. if (restart) {
  494. priv->dev->stats.rx_errors++;
  495. priv->dev->stats.rx_fifo_errors++;
  496. if (netif_msg_rx_err(priv) && net_ratelimit())
  497. printk(KERN_WARNING "%s: rx dma ring overrun\n",
  498. priv->dev->name);
  499.  
  500. if (unlikely((restart->dataflags & CPMAC_OWN) == 0)) {
  501. if (netif_msg_drv(priv))
  502. printk(KERN_ERR "%s: cpmac_poll is trying to "
  503. "restart rx from a descriptor that's "
  504. "not free: %p\n",
  505. priv->dev->name, restart);
  506. goto fatal_error;
  507. }
  508.  
  509. cpmac_write(priv->regs, CPMAC_RX_PTR(0), restart->mapping);
  510. }
  511.  
  512. priv->rx_head = desc;
  513. spin_unlock(&priv->rx_lock);
  514. if (unlikely(netif_msg_rx_status(priv)))
  515. printk(KERN_DEBUG "%s: poll processed %d packets\n",
  516. priv->dev->name, received);
  517. if (processed == 0) {
  518. /* we ran out of packets to read,
  519. * revert to interrupt-driven mode */
  520. napi_complete(napi);
  521. cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
  522. return 0;
  523. }
  524.  
  525. return 1;
  526.  
  527. fatal_error:
  528. /* Something went horribly wrong.
  529. * Reset hardware to try to recover rather than wedging. */
  530.  
  531. if (netif_msg_drv(priv)) {
  532. printk(KERN_ERR "%s: cpmac_poll is confused. "
  533. "Resetting hardware\n", priv->dev->name);
  534. cpmac_dump_all_desc(priv->dev);
  535. printk(KERN_DEBUG "%s: RX_PTR(0)=0x%08x RX_ACK(0)=0x%08x\n",
  536. priv->dev->name,
  537. cpmac_read(priv->regs, CPMAC_RX_PTR(0)),
  538. cpmac_read(priv->regs, CPMAC_RX_ACK(0)));
  539. }
  540.  
  541. spin_unlock(&priv->rx_lock);
  542. napi_complete(napi);
  543. netif_tx_stop_all_queues(priv->dev);
  544. napi_disable(&priv->napi);
  545.  
  546. atomic_inc(&priv->reset_pending);
  547. cpmac_hw_stop(priv->dev);
  548. if (!schedule_work(&priv->reset_work))
  549. atomic_dec(&priv->reset_pending);
  550. return 0;
  551.  
  552. }
  553.  
  554. static int cpmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
  555. {
  556. int queue, len;
  557. struct cpmac_desc *desc;
  558. struct cpmac_priv *priv = netdev_priv(dev);
  559.  
  560. if (unlikely(atomic_read(&priv->reset_pending)))
  561. return NETDEV_TX_BUSY;
  562.  
  563. if (unlikely(skb_padto(skb, ETH_ZLEN)))
  564. return NETDEV_TX_OK;
  565.  
  566. len = max(skb->len, ETH_ZLEN);
  567. queue = skb_get_queue_mapping(skb);
  568. netif_stop_subqueue(dev, queue);
  569.  
  570. desc = &priv->desc_ring[queue];
  571. if (unlikely(desc->dataflags & CPMAC_OWN)) {
  572. if (netif_msg_tx_err(priv) && net_ratelimit())
  573. printk(KERN_WARNING "%s: tx dma ring full\n",
  574. dev->name);
  575. return NETDEV_TX_BUSY;
  576. }
  577.  
  578. spin_lock(&priv->lock);
  579. spin_unlock(&priv->lock);
  580. desc->dataflags = CPMAC_SOP | CPMAC_EOP | CPMAC_OWN;
  581. desc->skb = skb;
  582. desc->data_mapping = dma_map_single(&dev->dev, skb->data, len,
  583. DMA_TO_DEVICE);
  584. desc->hw_data = (u32)desc->data_mapping;
  585. desc->datalen = len;
  586. desc->buflen = len;
  587. if (unlikely(netif_msg_tx_queued(priv)))
  588. printk(KERN_DEBUG "%s: sending 0x%p, len=%d\n", dev->name, skb,
  589. skb->len);
  590. if (unlikely(netif_msg_hw(priv)))
  591. cpmac_dump_desc(dev, desc);
  592. if (unlikely(netif_msg_pktdata(priv)))
  593. cpmac_dump_skb(dev, skb);
  594. cpmac_write(priv->regs, CPMAC_TX_PTR(queue), (u32)desc->mapping);
  595.  
  596. return NETDEV_TX_OK;
  597. }
  598.  
  599. static void cpmac_end_xmit(struct net_device *dev, int queue)
  600. {
  601. struct cpmac_desc *desc;
  602. struct cpmac_priv *priv = netdev_priv(dev);
  603.  
  604. desc = &priv->desc_ring[queue];
  605. cpmac_write(priv->regs, CPMAC_TX_ACK(queue), (u32)desc->mapping);
  606. if (likely(desc->skb)) {
  607. spin_lock(&priv->lock);
  608. dev->stats.tx_packets++;
  609. dev->stats.tx_bytes += desc->skb->len;
  610. spin_unlock(&priv->lock);
  611. dma_unmap_single(&dev->dev, desc->data_mapping, desc->skb->len,
  612. DMA_TO_DEVICE);
  613.  
  614. if (unlikely(netif_msg_tx_done(priv)))
  615. printk(KERN_DEBUG "%s: sent 0x%p, len=%d\n", dev->name,
  616. desc->skb, desc->skb->len);
  617.  
  618. dev_kfree_skb_irq(desc->skb);
  619. desc->skb = NULL;
  620. if (__netif_subqueue_stopped(dev, queue))
  621. netif_wake_subqueue(dev, queue);
  622. } else {
  623. if (netif_msg_tx_err(priv) && net_ratelimit())
  624. printk(KERN_WARNING
  625. "%s: end_xmit: spurious interrupt\n", dev->name);
  626. if (__netif_subqueue_stopped(dev, queue))
  627. netif_wake_subqueue(dev, queue);
  628. }
  629. }
  630.  
  631. static void cpmac_hw_stop(struct net_device *dev)
  632. {
  633. int i;
  634. struct cpmac_priv *priv = netdev_priv(dev);
  635. struct plat_cpmac_data *pdata = priv->pdev->dev.platform_data;
  636.  
  637. ar7_device_reset(pdata->reset_bit);
  638. cpmac_write(priv->regs, CPMAC_RX_CONTROL,
  639. cpmac_read(priv->regs, CPMAC_RX_CONTROL) & ~1);
  640. cpmac_write(priv->regs, CPMAC_TX_CONTROL,
  641. cpmac_read(priv->regs, CPMAC_TX_CONTROL) & ~1);
  642. for (i = 0; i < 8; i++) {
  643. cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
  644. cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
  645. }
  646. cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
  647. cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
  648. cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
  649. cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
  650. cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
  651. cpmac_read(priv->regs, CPMAC_MAC_CONTROL) & ~MAC_MII);
  652. }
  653.  
  654. static void cpmac_hw_start(struct net_device *dev)
  655. {
  656. int i;
  657. struct cpmac_priv *priv = netdev_priv(dev);
  658. struct plat_cpmac_data *pdata = priv->pdev->dev.platform_data;
  659.  
  660. ar7_device_reset(pdata->reset_bit);
  661. for (i = 0; i < 8; i++) {
  662. cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
  663. cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
  664. }
  665. cpmac_write(priv->regs, CPMAC_RX_PTR(0), priv->rx_head->mapping);
  666.  
  667. cpmac_write(priv->regs, CPMAC_MBP, MBP_RXSHORT | MBP_RXBCAST |
  668. MBP_RXMCAST);
  669. cpmac_write(priv->regs, CPMAC_BUFFER_OFFSET, 0);
  670. for (i = 0; i < 8; i++)
  671. cpmac_write(priv->regs, CPMAC_MAC_ADDR_LO(i), dev->dev_addr[5]);
  672. cpmac_write(priv->regs, CPMAC_MAC_ADDR_MID, dev->dev_addr[4]);
  673. cpmac_write(priv->regs, CPMAC_MAC_ADDR_HI, be32_to_cpu(*(u32 *)
  674. dev->dev_addr));
  675. cpmac_write(priv->regs, CPMAC_MAX_LENGTH, CPMAC_SKB_SIZE);
  676. cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
  677. cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
  678. cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
  679. cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
  680. cpmac_write(priv->regs, CPMAC_UNICAST_ENABLE, 1);
  681. cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
  682. cpmac_write(priv->regs, CPMAC_TX_INT_ENABLE, 0xff);
  683. cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);
  684.  
  685. cpmac_write(priv->regs, CPMAC_RX_CONTROL,
  686. cpmac_read(priv->regs, CPMAC_RX_CONTROL) | 1);
  687. cpmac_write(priv->regs, CPMAC_TX_CONTROL,
  688. cpmac_read(priv->regs, CPMAC_TX_CONTROL) | 1);
  689. cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
  690. cpmac_read(priv->regs, CPMAC_MAC_CONTROL) | MAC_MII |
  691. MAC_FDX);
  692. }
  693.  
  694. static void cpmac_clear_rx(struct net_device *dev)
  695. {
  696. struct cpmac_priv *priv = netdev_priv(dev);
  697. struct cpmac_desc *desc;
  698. int i;
  699. if (unlikely(!priv->rx_head))
  700. return;
  701. desc = priv->rx_head;
  702. for (i = 0; i < priv->ring_size; i++) {
  703. if ((desc->dataflags & CPMAC_OWN) == 0) {
  704. if (netif_msg_rx_err(priv) && net_ratelimit())
  705. printk(KERN_WARNING "%s: packet dropped\n",
  706. dev->name);
  707. if (unlikely(netif_msg_hw(priv)))
  708. cpmac_dump_desc(dev, desc);
  709. desc->dataflags = CPMAC_OWN;
  710. dev->stats.rx_dropped++;
  711. }
  712. desc->hw_next = desc->next->mapping;
  713. desc = desc->next;
  714. }
  715. priv->rx_head->prev->hw_next = 0;
  716. }
  717.  
  718. static void cpmac_clear_tx(struct net_device *dev)
  719. {
  720. struct cpmac_priv *priv = netdev_priv(dev);
  721. int i;
  722. if (unlikely(!priv->desc_ring))
  723. return;
  724. for (i = 0; i < CPMAC_QUEUES; i++) {
  725. priv->desc_ring[i].dataflags = 0;
  726. if (priv->desc_ring[i].skb) {
  727. dev_kfree_skb_any(priv->desc_ring[i].skb);
  728. priv->desc_ring[i].skb = NULL;
  729. }
  730. }
  731. }
  732.  
  733. static void cpmac_hw_error(struct work_struct *work)
  734. {
  735. struct cpmac_priv *priv =
  736. container_of(work, struct cpmac_priv, reset_work);
  737.  
  738. spin_lock(&priv->rx_lock);
  739. cpmac_clear_rx(priv->dev);
  740. spin_unlock(&priv->rx_lock);
  741. cpmac_clear_tx(priv->dev);
  742. cpmac_hw_start(priv->dev);
  743. barrier();
  744. atomic_dec(&priv->reset_pending);
  745.  
  746. netif_tx_wake_all_queues(priv->dev);
  747. cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);
  748. }
  749.  
  750. static void cpmac_check_status(struct net_device *dev)
  751. {
  752. struct cpmac_priv *priv = netdev_priv(dev);
  753.  
  754. u32 macstatus = cpmac_read(priv->regs, CPMAC_MAC_STATUS);
  755. int rx_channel = (macstatus >> 8) & 7;
  756. int rx_code = (macstatus >> 12) & 15;
  757. int tx_channel = (macstatus >> 16) & 7;
  758. int tx_code = (macstatus >> 20) & 15;
  759.  
  760. if (rx_code || tx_code) {
  761. if (netif_msg_drv(priv) && net_ratelimit()) {
  762. /* Can't find any documentation on what these
  763. *error codes actually are. So just log them and hope..
  764. */
  765. if (rx_code)
  766. printk(KERN_WARNING "%s: host error %d on rx "
  767. "channel %d (macstatus %08x), resetting\n",
  768. dev->name, rx_code, rx_channel, macstatus);
  769. if (tx_code)
  770. printk(KERN_WARNING "%s: host error %d on tx "
  771. "channel %d (macstatus %08x), resetting\n",
  772. dev->name, tx_code, tx_channel, macstatus);
  773. }
  774.  
  775. netif_tx_stop_all_queues(dev);
  776. cpmac_hw_stop(dev);
  777. if (schedule_work(&priv->reset_work))
  778. atomic_inc(&priv->reset_pending);
  779. if (unlikely(netif_msg_hw(priv)))
  780. cpmac_dump_regs(dev);
  781. }
  782. cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
  783. }
  784.  
  785. static irqreturn_t cpmac_irq(int irq, void *dev_id)
  786. {
  787. struct net_device *dev = dev_id;
  788. struct cpmac_priv *priv;
  789. int queue;
  790. u32 status;
  791.  
  792. priv = netdev_priv(dev);
  793.  
  794. status = cpmac_read(priv->regs, CPMAC_MAC_INT_VECTOR);
  795.  
  796. if (unlikely(netif_msg_intr(priv)))
  797. printk(KERN_DEBUG "%s: interrupt status: 0x%08x\n", dev->name,
  798. status);
  799.  
  800. if (status & MAC_INT_TX)
  801. cpmac_end_xmit(dev, (status & 7));
  802.  
  803. if (status & MAC_INT_RX) {
  804. queue = (status >> 8) & 7;
  805. if (napi_schedule_prep(&priv->napi)) {
  806. cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 1 << queue);
  807. __napi_schedule(&priv->napi);
  808. }
  809. }
  810.  
  811. cpmac_write(priv->regs, CPMAC_MAC_EOI_VECTOR, 0);
  812.  
  813. if (unlikely(status & (MAC_INT_HOST | MAC_INT_STATUS)))
  814. cpmac_check_status(dev);
  815.  
  816. return IRQ_HANDLED;
  817. }
  818.  
  819. static void cpmac_tx_timeout(struct net_device *dev)
  820. {
  821. struct cpmac_priv *priv = netdev_priv(dev);
  822.  
  823. spin_lock(&priv->lock);
  824. dev->stats.tx_errors++;
  825. spin_unlock(&priv->lock);
  826. if (netif_msg_tx_err(priv) && net_ratelimit())
  827. printk(KERN_WARNING "%s: transmit timeout\n", dev->name);
  828.  
  829. atomic_inc(&priv->reset_pending);
  830. barrier();
  831. cpmac_clear_tx(dev);
  832. barrier();
  833. atomic_dec(&priv->reset_pending);
  834.  
  835. netif_tx_wake_all_queues(priv->dev);
  836. }
  837.  
  838. static int cpmac_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  839. {
  840. struct cpmac_priv *priv = netdev_priv(dev);
  841. if (!(netif_running(dev)))
  842. return -EINVAL;
  843. if (!priv->phy)
  844. return -EINVAL;
  845.  
  846. return phy_mii_ioctl(priv->phy, ifr, cmd);
  847. }
  848.  
  849. static int cpmac_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  850. {
  851. struct cpmac_priv *priv = netdev_priv(dev);
  852.  
  853. if (priv->phy)
  854. return phy_ethtool_gset(priv->phy, cmd);
  855.  
  856. return -EINVAL;
  857. }
  858.  
  859. static int cpmac_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  860. {
  861. struct cpmac_priv *priv = netdev_priv(dev);
  862.  
  863. if (!capable(CAP_NET_ADMIN))
  864. return -EPERM;
  865.  
  866. if (priv->phy)
  867. return phy_ethtool_sset(priv->phy, cmd);
  868.  
  869. return -EINVAL;
  870. }
  871.  
  872. static void cpmac_get_ringparam(struct net_device *dev,
  873. struct ethtool_ringparam *ring)
  874. {
  875. struct cpmac_priv *priv = netdev_priv(dev);
  876.  
  877. ring->rx_max_pending = 1024;
  878. ring->rx_mini_max_pending = 1;
  879. ring->rx_jumbo_max_pending = 1;
  880. ring->tx_max_pending = 1;
  881.  
  882. ring->rx_pending = priv->ring_size;
  883. ring->rx_mini_pending = 1;
  884. ring->rx_jumbo_pending = 1;
  885. ring->tx_pending = 1;
  886. }
  887.  
  888. static int cpmac_set_ringparam(struct net_device *dev,
  889. struct ethtool_ringparam *ring)
  890. {
  891. struct cpmac_priv *priv = netdev_priv(dev);
  892.  
  893. if (netif_running(dev))
  894. return -EBUSY;
  895. priv->ring_size = ring->rx_pending;
  896. return 0;
  897. }
  898.  
  899. static void cpmac_get_drvinfo(struct net_device *dev,
  900. struct ethtool_drvinfo *info)
  901. {
  902. strlcpy(info->driver, "cpmac", sizeof(info->driver));
  903. strlcpy(info->version, CPMAC_VERSION, sizeof(info->version));
  904. snprintf(info->bus_info, sizeof(info->bus_info), "%s", "cpmac");
  905. info->regdump_len = 0;
  906. }
  907.  
  908. static const struct ethtool_ops cpmac_ethtool_ops = {
  909. .get_settings = cpmac_get_settings,
  910. .set_settings = cpmac_set_settings,
  911. .get_drvinfo = cpmac_get_drvinfo,
  912. .get_link = ethtool_op_get_link,
  913. .get_ringparam = cpmac_get_ringparam,
  914. .set_ringparam = cpmac_set_ringparam,
  915. };
  916.  
  917. static void cpmac_adjust_link(struct net_device *dev)
  918. {
  919. struct cpmac_priv *priv = netdev_priv(dev);
  920. int new_state = 0;
  921.  
  922. spin_lock(&priv->lock);
  923. if (priv->phy->link) {
  924. netif_tx_start_all_queues(dev);
  925. if (priv->phy->duplex != priv->oldduplex) {
  926. new_state = 1;
  927. priv->oldduplex = priv->phy->duplex;
  928. }
  929.  
  930. if (priv->phy->speed != priv->oldspeed) {
  931. new_state = 1;
  932. priv->oldspeed = priv->phy->speed;
  933. }
  934.  
  935. if (!priv->oldlink) {
  936. new_state = 1;
  937. priv->oldlink = 1;
  938. }
  939. } else if (priv->oldlink) {
  940. new_state = 1;
  941. priv->oldlink = 0;
  942. priv->oldspeed = 0;
  943. priv->oldduplex = -1;
  944. }
  945.  
  946. if (new_state && netif_msg_link(priv) && net_ratelimit())
  947. phy_print_status(priv->phy);
  948.  
  949. spin_unlock(&priv->lock);
  950. }
  951.  
  952. static int cpmac_open(struct net_device *dev)
  953. {
  954. int i, size, res;
  955. struct cpmac_priv *priv = netdev_priv(dev);
  956. struct resource *mem;
  957. struct cpmac_desc *desc;
  958. struct sk_buff *skb;
  959.  
  960. mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
  961. if (!request_mem_region(mem->start, resource_size(mem), dev->name)) {
  962. if (netif_msg_drv(priv))
  963. printk(KERN_ERR "%s: failed to request registers\n",
  964. dev->name);
  965. res = -ENXIO;
  966. goto fail_reserve;
  967. }
  968.  
  969. priv->regs = ioremap(mem->start, resource_size(mem));
  970. if (!priv->regs) {
  971. if (netif_msg_drv(priv))
  972. printk(KERN_ERR "%s: failed to remap registers\n",
  973. dev->name);
  974. res = -ENXIO;
  975. goto fail_remap;
  976. }
  977.  
  978. size = priv->ring_size + CPMAC_QUEUES;
  979. priv->desc_ring = dma_alloc_coherent(&dev->dev,
  980. sizeof(struct cpmac_desc) * size,
  981. &priv->dma_ring,
  982. GFP_KERNEL);
  983. if (!priv->desc_ring) {
  984. res = -ENOMEM;
  985. goto fail_alloc;
  986. }
  987.  
  988. for (i = 0; i < size; i++)
  989. priv->desc_ring[i].mapping = priv->dma_ring + sizeof(*desc) * i;
  990.  
  991. priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
  992. for (i = 0, desc = priv->rx_head; i < priv->ring_size; i++, desc++) {
  993. skb = netdev_alloc_skb_ip_align(dev, CPMAC_SKB_SIZE);
  994. if (unlikely(!skb)) {
  995. res = -ENOMEM;
  996. goto fail_desc;
  997. }
  998. desc->skb = skb;
  999. desc->data_mapping = dma_map_single(&dev->dev, skb->data,
  1000. CPMAC_SKB_SIZE,
  1001. DMA_FROM_DEVICE);
  1002. desc->hw_data = (u32)desc->data_mapping;
  1003. desc->buflen = CPMAC_SKB_SIZE;
  1004. desc->dataflags = CPMAC_OWN;
  1005. desc->next = &priv->rx_head[(i + 1) % priv->ring_size];
  1006. desc->next->prev = desc;
  1007. desc->hw_next = (u32)desc->next->mapping;
  1008. }
  1009.  
  1010. priv->rx_head->prev->hw_next = (u32)0;
  1011.  
  1012. res = request_irq(dev->irq, cpmac_irq, IRQF_SHARED, dev->name, dev);
  1013. if (res) {
  1014. if (netif_msg_drv(priv))
  1015. printk(KERN_ERR "%s: failed to obtain irq\n",
  1016. dev->name);
  1017. goto fail_irq;
  1018. }
  1019.  
  1020. atomic_set(&priv->reset_pending, 0);
  1021. INIT_WORK(&priv->reset_work, cpmac_hw_error);
  1022. cpmac_hw_start(dev);
  1023.  
  1024. napi_enable(&priv->napi);
  1025. priv->phy->state = PHY_CHANGELINK;
  1026. phy_start(priv->phy);
  1027.  
  1028. return 0;
  1029.  
  1030. fail_irq:
  1031. fail_desc:
  1032. for (i = 0; i < priv->ring_size; i++) {
  1033. if (priv->rx_head[i].skb) {
  1034. dma_unmap_single(&dev->dev,
  1035. priv->rx_head[i].data_mapping,
  1036. CPMAC_SKB_SIZE,
  1037. DMA_FROM_DEVICE);
  1038. kfree_skb(priv->rx_head[i].skb);
  1039. }
  1040. }
  1041. fail_alloc:
  1042. kfree(priv->desc_ring);
  1043. iounmap(priv->regs);
  1044.  
  1045. fail_remap:
  1046. release_mem_region(mem->start, resource_size(mem));
  1047.  
  1048. fail_reserve:
  1049. return res;
  1050. }
  1051.  
  1052. static int cpmac_stop(struct net_device *dev)
  1053. {
  1054. int i;
  1055. struct cpmac_priv *priv = netdev_priv(dev);
  1056. struct resource *mem;
  1057.  
  1058. netif_tx_stop_all_queues(dev);
  1059.  
  1060. cancel_work_sync(&priv->reset_work);
  1061. napi_disable(&priv->napi);
  1062. phy_stop(priv->phy);
  1063.  
  1064. cpmac_hw_stop(dev);
  1065.  
  1066. for (i = 0; i < 8; i++)
  1067. cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
  1068. cpmac_write(priv->regs, CPMAC_RX_PTR(0), 0);
  1069. cpmac_write(priv->regs, CPMAC_MBP, 0);
  1070.  
  1071. free_irq(dev->irq, dev);
  1072. iounmap(priv->regs);
  1073. mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
  1074. release_mem_region(mem->start, resource_size(mem));
  1075. priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
  1076. for (i = 0; i < priv->ring_size; i++) {
  1077. if (priv->rx_head[i].skb) {
  1078. dma_unmap_single(&dev->dev,
  1079. priv->rx_head[i].data_mapping,
  1080. CPMAC_SKB_SIZE,
  1081. DMA_FROM_DEVICE);
  1082. kfree_skb(priv->rx_head[i].skb);
  1083. }
  1084. }
  1085.  
  1086. dma_free_coherent(&dev->dev, sizeof(struct cpmac_desc) *
  1087. (CPMAC_QUEUES + priv->ring_size),
  1088. priv->desc_ring, priv->dma_ring);
  1089. return 0;
  1090. }
  1091.  
  1092. static const struct net_device_ops cpmac_netdev_ops = {
  1093. .ndo_open = cpmac_open,
  1094. .ndo_stop = cpmac_stop,
  1095. .ndo_start_xmit = cpmac_start_xmit,
  1096. .ndo_tx_timeout = cpmac_tx_timeout,
  1097. .ndo_set_rx_mode = cpmac_set_multicast_list,
  1098. .ndo_do_ioctl = cpmac_ioctl,
  1099. .ndo_set_config = cpmac_config,
  1100. .ndo_change_mtu = eth_change_mtu,
  1101. .ndo_validate_addr = eth_validate_addr,
  1102. .ndo_set_mac_address = eth_mac_addr,
  1103. };
  1104.  
  1105. static int external_switch;
  1106.  
  1107. static int cpmac_probe(struct platform_device *pdev)
  1108. {
  1109. int rc, phy_id;
  1110. char mdio_bus_id[MII_BUS_ID_SIZE];
  1111. struct resource *mem;
  1112. struct cpmac_priv *priv;
  1113. struct net_device *dev;
  1114. struct plat_cpmac_data *pdata;
  1115.  
  1116. pdata = pdev->dev.platform_data;
  1117.  
  1118. for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
  1119. if (!(pdata->phy_mask & (1 << phy_id)))
  1120. continue;
  1121. if (!cpmac_mii->phy_map[phy_id])
  1122. continue;
  1123. strncpy(mdio_bus_id, cpmac_mii->id, MII_BUS_ID_SIZE);
  1124. break;
  1125. }
  1126.  
  1127. if (phy_id == PHY_MAX_ADDR && pdev->id == 1) {
  1128. printk(KERN_ERR "cpmac: No PHY present, using fixed PHY\n");
  1129. phy_id = pdev->id;
  1130. strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
  1131. }
  1132.  
  1133. dev = alloc_etherdev_mq(sizeof(*priv), CPMAC_QUEUES);
  1134. if (!dev)
  1135. return -ENOMEM;
  1136.  
  1137. platform_set_drvdata(pdev, dev);
  1138. priv = netdev_priv(dev);
  1139.  
  1140. priv->pdev = pdev;
  1141. mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
  1142. if (!mem) {
  1143. rc = -ENODEV;
  1144. goto fail;
  1145. }
  1146.  
  1147. ar7_device_reset(pdata->reset_bit);
  1148.  
  1149. dev->irq = platform_get_irq_byname(pdev, "irq");
  1150.  
  1151. dev->netdev_ops = &cpmac_netdev_ops;
  1152. dev->ethtool_ops = &cpmac_ethtool_ops;
  1153.  
  1154. netif_napi_add(dev, &priv->napi, cpmac_poll, 64);
  1155.  
  1156. spin_lock_init(&priv->lock);
  1157. spin_lock_init(&priv->rx_lock);
  1158. priv->dev = dev;
  1159. priv->ring_size = 64;
  1160. priv->msg_enable = netif_msg_init(debug_level, 0xff);
  1161. memcpy(dev->dev_addr, pdata->dev_addr, sizeof(pdata->dev_addr));
  1162.  
  1163. snprintf(priv->phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT,
  1164. mdio_bus_id, phy_id);
  1165.  
  1166. rc = register_netdev(dev);
  1167. if (rc) {
  1168. printk(KERN_ERR "cpmac: error %i registering device %s\n", rc,
  1169. dev->name);
  1170. goto fail;
  1171. }
  1172.  
  1173. priv->phy = phy_connect(dev, priv->phy_name, cpmac_adjust_link,
  1174. PHY_INTERFACE_MODE_MII);
  1175.  
  1176. if (IS_ERR(priv->phy)) {
  1177. if (netif_msg_drv(priv))
  1178. printk(KERN_ERR "%s: Could not attach to PHY\n",
  1179. dev->name);
  1180. rc = PTR_ERR(priv->phy);
  1181. goto fail;
  1182. }
  1183.  
  1184. if (netif_msg_probe(priv)) {
  1185. printk(KERN_INFO
  1186. "cpmac: device %s (regs: %p, irq: %d, phy: %s, "
  1187. "mac: %pM)\n", dev->name, (void *)mem->start, dev->irq,
  1188. priv->phy_name, dev->dev_addr);
  1189. }
  1190. return 0;
  1191.  
  1192. fail:
  1193. free_netdev(dev);
  1194. return rc;
  1195. }
  1196.  
  1197. static int cpmac_remove(struct platform_device *pdev)
  1198. {
  1199. struct net_device *dev = platform_get_drvdata(pdev);
  1200. unregister_netdev(dev);
  1201. free_netdev(dev);
  1202. return 0;
  1203. }
  1204.  
  1205. static struct platform_driver cpmac_driver = {
  1206. .driver.name = "cpmac",
  1207. .driver.owner = THIS_MODULE,
  1208. .probe = cpmac_probe,
  1209. .remove = cpmac_remove,
  1210. };
  1211.  
  1212. int cpmac_init(void)
  1213. {
  1214. u32 mask;
  1215. int i, res;
  1216. void __iomem *mii_reg;
  1217.  
  1218. cpmac_mii = mdiobus_alloc();
  1219. if (cpmac_mii == NULL)
  1220. return -ENOMEM;
  1221.  
  1222. cpmac_mii->name = "cpmac-mii";
  1223. cpmac_mii->read = cpmac_mdio_read;
  1224. cpmac_mii->write = cpmac_mdio_write;
  1225. cpmac_mii->reset = cpmac_mdio_reset;
  1226. cpmac_mii->irq = mii_irqs;
  1227.  
  1228. cpmac_mii->priv = ioremap(ar7_is_titan() ? TITAN_REGS_MDIO : AR7_REGS_MDIO, 256);
  1229.  
  1230. if (!cpmac_mii->priv) {
  1231. printk(KERN_ERR "Can't ioremap mdio registers\n");
  1232. res = -ENXIO;
  1233. goto fail_alloc;
  1234. }
  1235.  
  1236. #warning FIXME: unhardcode gpio&reset bits
  1237. ar7_gpio_disable(26);
  1238. ar7_gpio_disable(27);
  1239.  
  1240. if (ar7_is_titan()) {
  1241. ar7_device_reset(AR7_RESET_BIT_EPHY);
  1242. ar7_device_reset(TITAN_RESET_BIT_EPHY1);
  1243. } else {
  1244. ar7_device_reset(AR7_RESET_BIT_EPHY);
  1245. ar7_device_reset(AR7_RESET_BIT_CPMAC_LO);
  1246. ar7_device_reset(AR7_RESET_BIT_CPMAC_HI);
  1247. }
  1248.  
  1249. cpmac_mii->reset(cpmac_mii);
  1250.  
  1251. for (i = 0; i < 300; i++) {
  1252. mask = cpmac_read(cpmac_mii->priv, CPMAC_MDIO_ALIVE);
  1253. mask &= ar7_is_titan()? ~(0x80000000 | 0x40000000) : ~(0x80000000);
  1254. if (mask)
  1255. break;
  1256. else
  1257. msleep(10);
  1258. }
  1259.  
  1260. if (mask & (mask - 1)) {
  1261. external_switch = 1;
  1262. if (!ar7_has_high_cpmac()) {
  1263. if (ar7_is_titan()) {
  1264. ar7_device_disable(AR7_RESET_BIT_EPHY);
  1265. ar7_device_disable(TITAN_RESET_BIT_EPHY1);
  1266. } else
  1267. ar7_device_disable(AR7_RESET_BIT_EPHY);
  1268.  
  1269. //Titan remap might be different
  1270. mii_reg = ioremap(AR7_REGS_MII, 4);
  1271. if (mii_reg) {
  1272. writel(readl(mii_reg) | 1, mii_reg);
  1273. iounmap(mii_reg);
  1274. }
  1275. }
  1276. }
  1277.  
  1278. if (external_switch)
  1279. printk(KERN_INFO "EXTERNAL SWITCH!!!\n");
  1280. else if (mask)
  1281. printk(KERN_INFO "EXTERNAL PHY!!!\n");
  1282. else
  1283. printk(KERN_INFO "INTERNAL PHY!!!\n");
  1284.  
  1285. if (ar7_is_titan())
  1286. cpmac_mii->phy_mask = ~(mask | 0x80000000 | 0x40000000);
  1287. else
  1288. cpmac_mii->phy_mask = ~(mask | 0x80000000);
  1289.  
  1290. snprintf(cpmac_mii->id, MII_BUS_ID_SIZE, "cpmac-1");
  1291.  
  1292. res = mdiobus_register(cpmac_mii);
  1293. if (res)
  1294. goto fail_mii;
  1295.  
  1296. res = platform_driver_register(&cpmac_driver);
  1297. if (res)
  1298. goto fail_cpmac;
  1299.  
  1300. return 0;
  1301.  
  1302. fail_cpmac:
  1303. mdiobus_unregister(cpmac_mii);
  1304.  
  1305. fail_mii:
  1306. iounmap(cpmac_mii->priv);
  1307.  
  1308. fail_alloc:
  1309. mdiobus_free(cpmac_mii);
  1310.  
  1311. return res;
  1312. }
  1313.  
  1314. void cpmac_exit(void)
  1315. {
  1316. platform_driver_unregister(&cpmac_driver);
  1317. mdiobus_unregister(cpmac_mii);
  1318. iounmap(cpmac_mii->priv);
  1319. mdiobus_free(cpmac_mii);
  1320. }
  1321.  
  1322. module_init(cpmac_init);
  1323. module_exit(cpmac_exit);
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement
Public Pastes
Advertisement
We use cookies for various purposes including analytics. By continuing to use Pastebin, you agree to our use of cookies as described in the Cookies Policy.  OK, I Understand
Not a member of Pastebin yet?
Sign Up, it unlocks many cool features!