// Populate the pagetable
  int n;
  for(n=0;n<4096;n++)
  {
    if(n==0)
    {
      // SRAM.  Outer and inner write back, write allocate.
      //                                      BASE      TEX       AP        CB      SECTION
      *(volatile uint32_t *)(0x4000 + n*4) = (n<<20) | (1<<12) | (3<<10) | (3<<2) | 2;
    } else if (n>=0x400 && n<0xc00) {
      // DRAM. Outer and inner non-cacheable.
      *(volatile uint32_t *)(0x4000 + n*4) = (n<<20) | (1<<12) | (3<<10) | (0<<2) | 2;
    } else {
      // Other stuff. Non-shared device.
      *(volatile uint32_t *)(0x4000 + n*4) = (n<<20) | (2<<12) | (3<<10) | (0<<2) | 2;
    }
  }

  // Set up the pagetable
  asm("ldr r8, =0x4000; mcr p15, 0, r8, c2, c0, 0" : : : "r8");
  asm("mov r8, #0x3; mcr p15, 0, r8, c3, c0, 0" : : : "r8");

  // Enable MMU
  asm(
    "mrc p15, 0, r9, c1, c0, 0;"
    "orr r9, r9, #0x1;"
    "mcr p15, 0, r9, c1, c0, 0;"
    : : : "r9");