library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity CTL is
   port(
      mpy : in std_logic; -- input port declarations
      a, b : in std_logic_vector(7 downto 0);
      prod : out std_logic_vector(15 downto 0);
      rdy: out std_logic);

end CTL;

architecture behav of CTL is
type  state  is (WT, S1, S2, S3, S4, S5, S6, S7);  -- state type declaration
signal new_state : state;   -- new state signal variable

signal P: std_logic_vector(17 downto 0);
signal done: boolean;
signal clk: std_logic;
	begin
		process is
		begin
			clk<='0','1' after 20 ns;
			wait for 40 ns;
		end process;
   -- state transition process:
   process is

   variable curr_state: state := S7;

  		 begin
      if clk = '1' then
         case curr_state is
         -- state transition statements go here.
            when WT =>
			   if mpy = '1' then curr_state := S1;
               end if;
            when S1 =>
               if P(2 downto 0)="000" or P(2 downto 0)="111" then curr_state := S6;
   			   elsif P(2 downto 0)="001" or P(2 downto 0)="010" then curr_state := S2;
               elsif P(2 downto 0)="011" then curr_state := S3;
               elsif P(2 downto 0)="100" then curr_state := S4;
               elsif P(2 downto 0)="101" or P(2 downto 0)="110" then curr_state := S5;
               end if;
	    	when S2 =>
	    		curr_state := S6;
            when S3 =>
            	curr_state := S6;
            when S4 =>
            	curr_state := S6;
            when S5 =>
            	curr_state := S6;
            when S6 =>
            	if done = true then curr_state := S7;
            	elsif done = false then curr_state:=S1;
            	end if;
            when S7 =>
            	if mpy = '0' then curr_state := WT;
            	end if;
         end case;


      end if;

      new_state <= curr_state;
      wait on clk;
   end process;

   -- asserted outputs process:
   process is
   variable P_val: std_logic_vector(17 downto 0);
   variable prod_val: std_logic_vector(15 downto 0);
   variable I: std_logic_vector(1 downto 0);
   variable rdy_val : std_logic;
   variable done_val : boolean;
   variable M, NegM: std_logic_vector (8 downto 0);
   begin
      case new_state is
      -- assigned output values go here.
      when WT =>
      	P_val(17 downto 9) := "000000000";
      	P_val(8 downto 1) := a;
      	P_val(0) := '0';
      	M(8 downto 0) := ('0'&b);
      	NegM := not(M)+'1';
      	I := "00";
      	prod_val := "ZZZZZZZZZZZZZZZZ";
      	rdy_val := '1';
      when S1 =>
        done_val := I="11";
        I := I + '1';

      when S2 =>
      	P_val(17 downto 9) := P_val(17 downto 9) + M(8 downto 0);
      when S3 =>
      	P_val(17 downto 9) := P_val(17 downto 9) + (M(8 downto 0) sll 1);
      when S4 =>
      	P_val(17 downto 9) := P_val(17 downto 9) + (NegM(8 downto 0) sll 1);
      when S5 =>
      	P_val(17 downto 9) := P_val(17 downto 9) + NegM(8 downto 0);
      when S6 =>
      	P_val:= (P sra 2);
      when S7 =>
      	prod_val := P_val(16 downto 1);
      	rdy_val := '1';


      end case;
      P<=P_val;
      prod<=prod_val;
      rdy<=rdy_val;
      done<=done_val;
      wait on new_state;  -- sensitivity list to restart process
   end process;
end behav;