Przerwanie SPI

ISR(SPIC_INT_vect)
{
    uint8_t d = SPIC_DATA;

    switch (state)
    {
        case 0:
            if (d==120) state = 1;
            break;
        case 1:
            count = d;
            state = 2;
            break;
        case 2:
            if (d != (count ^ 120))
            {
                state = 0;
            }
            else
            {
                DMA.CH0.DESTADDR0 = (uintptr_t)&(dcc_buffer[nextBuffer].data);
                DMA.CH0.DESTADDR1 = (uintptr_t)&(dcc_buffer[nextBuffer].data)>>8;
                DMA.CH0.DESTADDR2 = 0;

                dcc_buffer[nextBuffer].write_flag = 1;
                dcc_buffer[nextBuffer].size = count;
                if (d==0)
                {
                    DMA_CH0_TRFCNT = 256;
                    DMA_CH1_TRFCNT = 256;
                }
                else
                {
                    DMA_CH0_TRFCNT = (uint16_t)count;
                    DMA_CH1_TRFCNT = (uint16_t)count;
                }
                DMA_CH0_CTRLA |= DMA_CH_ENABLE_bm;
                DMA_CH1_CTRLA |= DMA_CH_ENABLE_bm;

                state = 3;
            }
            break;
        case 3:
            if (--count>0) return;
            SPIC_DATA = CRC_CHECKSUM0;
            dcc_buffer[nextBuffer].crc = d;
            state = 4;
            break;
        case 4:
            SPIC_DATA = CRC_CHECKSUM1;
            dcc_buffer[nextBuffer].crc += d<<8;
            dcc_buffer[nextBuffer].write_flag = 0;
            if (dcc_buffer[nextBuffer].crc == CRC_CHECKSUM0+(CRC_CHECKSUM1<<8))
                nextBuffer = (nextBuffer+1) % 3;
            CRC_CTRL = CRC_RESET_RESET0_gc;
            CRC_CTRL = CRC_SOURCE_DMAC1_gc;
            state = 0;
            break;
    }
}