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By: a guest on Dec 21st, 2012  |  syntax: C  |  size: 0.89 KB  |  views: 39  |  expires: Never
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  1. uint8_t adc_control(int channel) {
  2.         /* clkgate - reset first, then enable */
  3.         __REG_SET(HW_LRADC_CTRL0) = __BLOCK_SFTRST;
  4.         __REG_CLR(HW_LRADC_CTRL0) = __BLOCK_CLKGATE | __BLOCK_SFTRST;
  5.         /* divide by 2 */
  6.         __REG_SET(HW_LRADC_CTRL2) = HW_LRADC_CTRL2__DIVIDE_BY_TWO(1);
  7.         /* accumulate & samples */
  8.         HW_LRADC_CHx(channel) = (0 << HW_LRADC_CHx__ACCUMULATE) | (1 << HW_LRADC_CHx__NUM_SAMPLES_BP);
  9.         /* schedule */
  10.         __REG_CLR(HW_LRADC_CTRL1) = HW_LRADC_CTRL1__LRADCx_IRQ(channel);
  11.         __REG_SET(HW_LRADC_CTRL0) = HW_LRADC_CTRL0__SCHEDULE(channel);
  12.         /* wait */
  13.         while(!(HW_LRADC_CTRL1 & HW_LRADC_CTRL1__LRADCx_IRQ(channel)))
  14.         {
  15.             uart_tx("waiting for ADC completition...\r\n");
  16.         };
  17.         /* get value */
  18.         return (HW_LRADC_CHx(channel) & HW_LRADC_CHx__VALUE_BM) >> HW_LRADC_CHx__VALUE_BP;
  19. }