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a guest Mar 6th, 2011 96 Never
  1. Starting program: /home/lekernel/FPGATools/antares/build/test-router/test-router /home/lekernel/FPGATools/6slx4.acg.gz SLICE_X0Y59 A SLICE_X0Y59 A1
  2. Reading chip database...
  3. ...done.
  4.  
  5. Chip: xc6slx4tqg144-3
  6. Grid: 45x73
  7. Wires: 335639
  8. Tile types: 162
  9. Site types: 30
  10.  
  11. Start:
  12.   Tile: CLEXM_X1Y61
  13.   Site type: SLICEM
  14.   Pin is an output connected to CLEXM_X1Y61:M_A
  15. End:
  16.   Tile: CLEXM_X1Y61
  17.   Site type: SLICEM
  18.   Pin is an input connected to CLEXM_X1Y61:M_A1
  19.  
  20. Routing CLEXM_X1Y61:M_A -> CLEXM_X1Y61:M_A1...
  21. Routing succeeded in 4 iterations:
  22. pip CLEXM_X1Y61 CLEXM_LOGICIN_B29CLEXM_LOGICIN_B29 -> M_A1
  23. pip INT_X1Y61 LOGICOUT13 -> LOGICIN_B29
  24. pip CLEXM_X1Y61 M_AMUX -> CLEXM_LOGICOUT13CLEXM_LOGICOUT13
  25. pip CLEXM_X1Y61 M_A -> M_AMUX
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