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  1. diff --git a/drivers/net/can/spi/hi311x.c b/drivers/net/can/spi/hi311x.c
  2. new file mode 100644
  3. index 0000000..2a3d794
  4. --- /dev/null
  5. +++ b/drivers/net/can/spi/hi311x.c
  6. @@ -0,0 +1,1072 @@
  7. +/* CAN bus driver for Holt HI3110 CAN Controller with SPI Interface
  8. + *
  9. + * Copyright(C) Timesys Corporation 2016
  10. + *
  11. + * Based on Microchip 251x CAN Controller (mcp251x) Linux kernel driver
  12. + * Copyright 2009 Christian Pellegrin EVOL S.r.l.
  13. + * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved.
  14. + * Copyright 2006 Arcom Control Systems Ltd.
  15. + *
  16. + * Based on CAN bus driver for the CCAN controller written by
  17. + * - Sascha Hauer, Marc Kleine-Budde, Pengutronix
  18. + * - Simon Kallweit, intefo AG
  19. + * Copyright 2007
  20. + *
  21. + * This program is free software; you can redistribute it and/or modify
  22. + * it under the terms of the GNU General Public License version 2 as
  23. + * published by the Free Software Foundation.
  24. + */
  25. +
  26. +#include <linux/can/core.h>
  27. +#include <linux/can/dev.h>
  28. +#include <linux/can/led.h>
  29. +#include <linux/clk.h>
  30. +#include <linux/completion.h>
  31. +#include <linux/delay.h>
  32. +#include <linux/device.h>
  33. +#include <linux/dma-mapping.h>
  34. +#include <linux/freezer.h>
  35. +#include <linux/interrupt.h>
  36. +#include <linux/io.h>
  37. +#include <linux/kernel.h>
  38. +#include <linux/module.h>
  39. +#include <linux/netdevice.h>
  40. +#include <linux/of.h>
  41. +#include <linux/of_device.h>
  42. +#include <linux/platform_device.h>
  43. +#include <linux/regulator/consumer.h>
  44. +#include <linux/slab.h>
  45. +#include <linux/spi/spi.h>
  46. +#include <linux/uaccess.h>
  47. +
  48. +#define HI3110_MASTER_RESET 0x56
  49. +#define HI3110_READ_CTRL0 0xD2
  50. +#define HI3110_READ_CTRL1 0xD4
  51. +#define HI3110_READ_STATF 0xE2
  52. +#define HI3110_WRITE_CTRL0 0x14
  53. +#define HI3110_WRITE_CTRL1 0x16
  54. +#define HI3110_WRITE_INTE 0x1C
  55. +#define HI3110_WRITE_BTR0 0x18
  56. +#define HI3110_WRITE_BTR1 0x1A
  57. +#define HI3110_READ_BTR0 0xD6
  58. +#define HI3110_READ_BTR1 0xD8
  59. +#define HI3110_READ_INTF 0xDE
  60. +#define HI3110_READ_ERR 0xDC
  61. +#define HI3110_READ_FIFO_WOTIME 0x48
  62. +#define HI3110_WRITE_FIFO 0x12
  63. +#define HI3110_READ_MESSTAT 0xDA
  64. +#define HI3110_READ_REC 0xEA
  65. +#define HI3110_READ_TEC 0xEC
  66. +
  67. +#define HI3110_CTRL0_MODE_MASK (7 << 5)
  68. +#define HI3110_CTRL0_NORMAL_MODE (0 << 5)
  69. +#define HI3110_CTRL0_LOOPBACK_MODE (1 << 5)
  70. +#define HI3110_CTRL0_MONITOR_MODE (2 << 5)
  71. +#define HI3110_CTRL0_SLEEP_MODE (3 << 5)
  72. +#define HI3110_CTRL0_INIT_MODE (4 << 5)
  73. +
  74. +#define HI3110_CTRL1_TXEN BIT(7)
  75. +
  76. +#define HI3110_INT_RXTMP BIT(7)
  77. +#define HI3110_INT_RXFIFO BIT(6)
  78. +#define HI3110_INT_TXCPLT BIT(5)
  79. +#define HI3110_INT_BUSERR BIT(4)
  80. +#define HI3110_INT_MCHG BIT(3)
  81. +#define HI3110_INT_WAKEUP BIT(2)
  82. +#define HI3110_INT_F1MESS BIT(1)
  83. +#define HI3110_INT_F0MESS BIT(0)
  84. +
  85. +#define HI3110_ERR_BUSOFF BIT(7)
  86. +#define HI3110_ERR_TXERRP BIT(6)
  87. +#define HI3110_ERR_RXERRP BIT(5)
  88. +#define HI3110_ERR_BITERR BIT(4)
  89. +#define HI3110_ERR_FRMERR BIT(3)
  90. +#define HI3110_ERR_CRCERR BIT(2)
  91. +#define HI3110_ERR_ACKERR BIT(1)
  92. +#define HI3110_ERR_STUFERR BIT(0)
  93. +#define HI3110_ERR_PROTOCOL_MASK (0x1F)
  94. +#define HI3110_ERR_PASSIVE_MASK (0x60)
  95. +
  96. +#define HI3110_STAT_RXFMTY BIT(1)
  97. +#define HI3110_STAT_BUSOFF BIT(2)
  98. +#define HI3110_STAT_ERRP BIT(3)
  99. +#define HI3110_STAT_ERRW BIT(4)
  100. +
  101. +#define HI3110_BTR0_SJW_SHIFT 6
  102. +#define HI3110_BTR0_BRP_SHIFT 0
  103. +
  104. +#define HI3110_BTR1_SAMP_3PERBIT (1 << 7)
  105. +#define HI3110_BTR1_SAMP_1PERBIT (0 << 7)
  106. +#define HI3110_BTR1_TSEG2_SHIFT 4
  107. +#define HI3110_BTR1_TSEG1_SHIFT 0
  108. +
  109. +#define HI3110_FIFO_WOTIME_TAG_OFF 0
  110. +#define HI3110_FIFO_WOTIME_ID_OFF 1
  111. +#define HI3110_FIFO_WOTIME_DLC_OFF 5
  112. +#define HI3110_FIFO_WOTIME_DAT_OFF 6
  113. +
  114. +#define HI3110_FIFO_WOTIME_TAG_IDE BIT(7)
  115. +#define HI3110_FIFO_WOTIME_ID_RTR BIT(0)
  116. +
  117. +#define HI3110_FIFO_TAG_OFF 0
  118. +#define HI3110_FIFO_ID_OFF 1
  119. +#define HI3110_FIFO_STD_DLC_OFF 3
  120. +#define HI3110_FIFO_STD_DATA_OFF 4
  121. +#define HI3110_FIFO_EXT_DLC_OFF 5
  122. +#define HI3110_FIFO_EXT_DATA_OFF 6
  123. +
  124. +#define HI3110_CAN_MAX_DATA_LEN 8
  125. +#define HI3110_RX_BUF_LEN 15
  126. +#define HI3110_TX_STD_BUF_LEN 12
  127. +#define HI3110_TX_EXT_BUF_LEN 14
  128. +#define HI3110_CAN_FRAME_MAX_BITS 128
  129. +#define HI3110_EFF_FLAGS 0x18 /* IDE + SRR */
  130. +
  131. +#define HI3110_TX_ECHO_SKB_MAX 1
  132. +
  133. +#define HI3110_OST_DELAY_MS (10)
  134. +
  135. +#define DEVICE_NAME "hi3110"
  136. +
  137. +static int hi3110_enable_dma = 1; /* Enable SPI DMA. Default: 1 (On) */
  138. +module_param(hi3110_enable_dma, int, 0444);
  139. +MODULE_PARM_DESC(hi3110_enable_dma, "Enable SPI DMA. Default: 1 (On)");
  140. +
  141. +static const struct can_bittiming_const hi3110_bittiming_const = {
  142. +   .name = DEVICE_NAME,
  143. +   .tseg1_min = 2,
  144. +   .tseg1_max = 16,
  145. +   .tseg2_min = 2,
  146. +   .tseg2_max = 8,
  147. +   .sjw_max = 4,
  148. +   .brp_min = 1,
  149. +   .brp_max = 64,
  150. +   .brp_inc = 1,
  151. +};
  152. +
  153. +enum hi3110_model {
  154. +   CAN_HI3110_HI3110 = 0x3110,
  155. +};
  156. +
  157. +struct hi3110_priv {
  158. +   struct can_priv can;
  159. +   struct net_device *net;
  160. +   struct spi_device *spi;
  161. +   enum hi3110_model model;
  162. +
  163. +   struct mutex hi3110_lock; /* SPI device lock */
  164. +
  165. +   u8 *spi_tx_buf;
  166. +   u8 *spi_rx_buf;
  167. +   dma_addr_t spi_tx_dma;
  168. +   dma_addr_t spi_rx_dma;
  169. +
  170. +   struct sk_buff *tx_skb;
  171. +   int tx_len;
  172. +
  173. +   struct workqueue_struct *wq;
  174. +   struct work_struct tx_work;
  175. +   struct work_struct restart_work;
  176. +
  177. +   int force_quit;
  178. +   int after_suspend;
  179. +#define HI3110_AFTER_SUSPEND_UP 1
  180. +#define HI3110_AFTER_SUSPEND_DOWN 2
  181. +#define HI3110_AFTER_SUSPEND_POWER 4
  182. +#define HI3110_AFTER_SUSPEND_RESTART 8
  183. +   int restart_tx;
  184. +   struct regulator *power;
  185. +   struct regulator *transceiver;
  186. +   struct clk *clk;
  187. +};
  188. +
  189. +static void hi3110_clean(struct net_device *net)
  190. +{
  191. +   struct hi3110_priv *priv = netdev_priv(net);
  192. +
  193. +   if (priv->tx_skb || priv->tx_len)
  194. +       net->stats.tx_errors++;
  195. +   if (priv->tx_skb)
  196. +       dev_kfree_skb(priv->tx_skb);
  197. +   if (priv->tx_len)
  198. +       can_free_echo_skb(priv->net, 0);
  199. +   priv->tx_skb = NULL;
  200. +   priv->tx_len = 0;
  201. +}
  202. +
  203. +/* Note about handling of error return of hi3110_spi_trans: accessing
  204. + * registers via SPI is not really different conceptually than using
  205. + * normal I/O assembler instructions, although it's much more
  206. + * complicated from a practical POV. So it's not advisable to always
  207. + * check the return value of this function. Imagine that every
  208. + * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0)
  209. + * error();", it would be a great mess (well there are some situation
  210. + * when exception handling C++ like could be useful after all). So we
  211. + * just check that transfers are OK at the beginning of our
  212. + * conversation with the chip and to avoid doing really nasty things
  213. + * (like injecting bogus packets in the network stack).
  214. + */
  215. +static int hi3110_spi_trans(struct spi_device *spi, int len)
  216. +{
  217. +   struct hi3110_priv *priv = spi_get_drvdata(spi);
  218. +   struct spi_transfer t = {
  219. +       .tx_buf = priv->spi_tx_buf,
  220. +       .rx_buf = priv->spi_rx_buf,
  221. +       .len = len,
  222. +       .cs_change = 0,
  223. +   };
  224. +   struct spi_message m;
  225. +   int ret;
  226. +
  227. +   spi_message_init(&m);
  228. +
  229. +   if (hi3110_enable_dma) {
  230. +       t.tx_dma = priv->spi_tx_dma;
  231. +       t.rx_dma = priv->spi_rx_dma;
  232. +       m.is_dma_mapped = 1;
  233. +   }
  234. +
  235. +   spi_message_add_tail(&t, &m);
  236. +
  237. +   ret = spi_sync(spi, &m);
  238. +
  239. +   if (ret)
  240. +       dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret);
  241. +   return ret;
  242. +}
  243. +
  244. +static u8 hi3110_cmd(struct spi_device *spi, u8 command)
  245. +{
  246. +   struct hi3110_priv *priv = spi_get_drvdata(spi);
  247. +
  248. +   priv->spi_tx_buf[0] = command;
  249. +   dev_dbg(&spi->dev, "hi3110_cmd: %02X\n", command);
  250. +
  251. +   return hi3110_spi_trans(spi, 1);
  252. +}
  253. +
  254. +static u8 hi3110_read(struct spi_device *spi, u8 command)
  255. +{
  256. +   struct hi3110_priv *priv = spi_get_drvdata(spi);
  257. +   u8 val = 0;
  258. +
  259. +   priv->spi_tx_buf[0] = command;
  260. +   hi3110_spi_trans(spi, 2);
  261. +   val = priv->spi_rx_buf[1];
  262. +
  263. +   return val;
  264. +}
  265. +
  266. +static void hi3110_write(struct spi_device *spi, u8 reg, u8 val)
  267. +{
  268. +   struct hi3110_priv *priv = spi_get_drvdata(spi);
  269. +
  270. +   priv->spi_tx_buf[0] = reg;
  271. +   priv->spi_tx_buf[1] = val;
  272. +   hi3110_spi_trans(spi, 2);
  273. +}
  274. +
  275. +static void hi3110_hw_tx_frame(struct spi_device *spi, u8 *buf, int len)
  276. +{
  277. +   struct hi3110_priv *priv = spi_get_drvdata(spi);
  278. +
  279. +   priv->spi_tx_buf[0] = HI3110_WRITE_FIFO;
  280. +   memcpy(priv->spi_tx_buf + 1, buf, len);
  281. +   hi3110_spi_trans(spi, len + 1);
  282. +}
  283. +
  284. +static void hi3110_hw_tx(struct spi_device *spi, struct can_frame *frame)
  285. +{
  286. +   u8 buf[HI3110_TX_EXT_BUF_LEN];
  287. +
  288. +   buf[HI3110_FIFO_TAG_OFF] = 0;
  289. +
  290. +   if (frame->can_id & CAN_EFF_FLAG) {
  291. +       /* Extended frame */
  292. +       buf[HI3110_FIFO_ID_OFF] = (frame->can_id & CAN_EFF_MASK) >> 21;
  293. +       buf[HI3110_FIFO_ID_OFF + 1] =
  294. +           (((frame->can_id & CAN_EFF_MASK) >> 13) & 0xe0) |
  295. +           HI3110_EFF_FLAGS |
  296. +           (((frame->can_id & CAN_EFF_MASK) >> 15) & 0x07);
  297. +       buf[HI3110_FIFO_ID_OFF + 2] =
  298. +           (frame->can_id & CAN_EFF_MASK) >> 7;
  299. +       buf[HI3110_FIFO_ID_OFF + 3] =
  300. +           ((frame->can_id & CAN_EFF_MASK) << 1) |
  301. +           ((frame->can_id & CAN_RTR_FLAG) ? 1 : 0);
  302. +
  303. +       buf[HI3110_FIFO_EXT_DLC_OFF] = frame->can_dlc;
  304. +
  305. +       memcpy(buf + HI3110_FIFO_EXT_DATA_OFF,
  306. +              frame->data, frame->can_dlc);
  307. +
  308. +       hi3110_hw_tx_frame(spi, buf, HI3110_TX_EXT_BUF_LEN -
  309. +                  (HI3110_CAN_MAX_DATA_LEN - frame->can_dlc));
  310. +   } else {
  311. +       /* Standard frame */
  312. +       buf[HI3110_FIFO_ID_OFF] =   (frame->can_id & CAN_SFF_MASK) >> 3;
  313. +       buf[HI3110_FIFO_ID_OFF + 1] =
  314. +           ((frame->can_id & CAN_SFF_MASK) << 5) |
  315. +           ((frame->can_id & CAN_RTR_FLAG) ? (1 << 4) : 0);
  316. +
  317. +       buf[HI3110_FIFO_STD_DLC_OFF] = frame->can_dlc;
  318. +
  319. +       memcpy(buf + HI3110_FIFO_STD_DATA_OFF,
  320. +              frame->data, frame->can_dlc);
  321. +
  322. +       hi3110_hw_tx_frame(spi, buf, HI3110_TX_STD_BUF_LEN -
  323. +                  (HI3110_CAN_MAX_DATA_LEN - frame->can_dlc));
  324. +   }
  325. +}
  326. +
  327. +static void hi3110_hw_rx_frame(struct spi_device *spi, u8 *buf)
  328. +{
  329. +   struct hi3110_priv *priv = spi_get_drvdata(spi);
  330. +
  331. +   priv->spi_tx_buf[0] = HI3110_READ_FIFO_WOTIME;
  332. +   hi3110_spi_trans(spi, HI3110_RX_BUF_LEN);
  333. +   memcpy(buf, priv->spi_rx_buf + 1, HI3110_RX_BUF_LEN - 1);
  334. +}
  335. +
  336. +static void hi3110_hw_rx(struct spi_device *spi)
  337. +{
  338. +   struct hi3110_priv *priv = spi_get_drvdata(spi);
  339. +   struct sk_buff *skb;
  340. +   struct can_frame *frame;
  341. +   u8 buf[HI3110_RX_BUF_LEN - 1];
  342. +
  343. +   skb = alloc_can_skb(priv->net, &frame);
  344. +   if (!skb) {
  345. +       priv->net->stats.rx_dropped++;
  346. +       return;
  347. +   }
  348. +
  349. +   hi3110_hw_rx_frame(spi, buf);
  350. +   if (buf[HI3110_FIFO_WOTIME_TAG_OFF] & HI3110_FIFO_WOTIME_TAG_IDE) {
  351. +       /* IDE is recessive (1), indicating extended 29-bit frame */
  352. +       frame->can_id = CAN_EFF_FLAG;
  353. +       frame->can_id |=
  354. +        (buf[HI3110_FIFO_WOTIME_ID_OFF] << 21) |
  355. +        (((buf[HI3110_FIFO_WOTIME_ID_OFF + 1] & 0xE0) >> 5) << 18) |
  356. +        ((buf[HI3110_FIFO_WOTIME_ID_OFF + 1] & 0x07) << 15) |
  357. +        (buf[HI3110_FIFO_WOTIME_ID_OFF + 2] << 7) |
  358. +        (buf[HI3110_FIFO_WOTIME_ID_OFF + 3] >> 1);
  359. +   } else {
  360. +       /* IDE is dominant (0), frame indicating standard 11-bit */
  361. +       frame->can_id =
  362. +           (buf[HI3110_FIFO_WOTIME_ID_OFF] << 3) |
  363. +           ((buf[HI3110_FIFO_WOTIME_ID_OFF + 1] & 0xE0) >> 5);
  364. +   }
  365. +
  366. +   /* Data length */
  367. +   frame->can_dlc = get_can_dlc(buf[HI3110_FIFO_WOTIME_DLC_OFF] & 0x0F);
  368. +
  369. +   if (buf[HI3110_FIFO_WOTIME_ID_OFF + 3] & HI3110_FIFO_WOTIME_ID_RTR)
  370. +       frame->can_id |= CAN_RTR_FLAG;
  371. +   else
  372. +       memcpy(frame->data, buf + HI3110_FIFO_WOTIME_DAT_OFF,
  373. +              frame->can_dlc);
  374. +
  375. +   priv->net->stats.rx_packets++;
  376. +   priv->net->stats.rx_bytes += frame->can_dlc;
  377. +
  378. +   can_led_event(priv->net, CAN_LED_EVENT_RX);
  379. +
  380. +   netif_rx_ni(skb);
  381. +}
  382. +
  383. +static void hi3110_hw_sleep(struct spi_device *spi)
  384. +{
  385. +   hi3110_write(spi, HI3110_WRITE_CTRL0, HI3110_CTRL0_SLEEP_MODE);
  386. +}
  387. +
  388. +static netdev_tx_t hi3110_hard_start_xmit(struct sk_buff *skb,
  389. +                     struct net_device *net)
  390. +{
  391. +   struct hi3110_priv *priv = netdev_priv(net);
  392. +   struct spi_device *spi = priv->spi;
  393. +
  394. +   if (priv->tx_skb || priv->tx_len) {
  395. +       dev_err(&spi->dev, "hard_xmit called while tx busy\n");
  396. +       return NETDEV_TX_BUSY;
  397. +   }
  398. +
  399. +   if (can_dropped_invalid_skb(net, skb))
  400. +       return NETDEV_TX_OK;
  401. +
  402. +   netif_stop_queue(net);
  403. +   priv->tx_skb = skb;
  404. +   queue_work(priv->wq, &priv->tx_work);
  405. +
  406. +   return NETDEV_TX_OK;
  407. +}
  408. +
  409. +static int hi3110_do_set_mode(struct net_device *net, enum can_mode mode)
  410. +{
  411. +   struct hi3110_priv *priv = netdev_priv(net);
  412. +
  413. +   switch (mode) {
  414. +   case CAN_MODE_START:
  415. +       hi3110_clean(net);
  416. +       /* We have to delay work since SPI I/O may sleep */
  417. +       priv->can.state = CAN_STATE_ERROR_ACTIVE;
  418. +       priv->restart_tx = 1;
  419. +       if (priv->can.restart_ms == 0)
  420. +           priv->after_suspend = HI3110_AFTER_SUSPEND_RESTART;
  421. +       queue_work(priv->wq, &priv->restart_work);
  422. +       break;
  423. +   default:
  424. +       return -EOPNOTSUPP;
  425. +   }
  426. +
  427. +   return 0;
  428. +}
  429. +
  430. +static int hi3110_get_berr_counter(const struct net_device *net,
  431. +                  struct can_berr_counter *bec)
  432. +{
  433. +   struct hi3110_priv *priv = netdev_priv(net);
  434. +   struct spi_device *spi = priv->spi;
  435. +
  436. +   bec->txerr = hi3110_read(spi, HI3110_READ_TEC);
  437. +   bec->rxerr = hi3110_read(spi, HI3110_READ_REC);
  438. +
  439. +   return 0;
  440. +}
  441. +
  442. +static int hi3110_set_normal_mode(struct spi_device *spi)
  443. +{
  444. +   struct hi3110_priv *priv = spi_get_drvdata(spi);
  445. +   u8 reg = 0;
  446. +
  447. +   hi3110_write(spi, HI3110_WRITE_INTE, HI3110_INT_BUSERR |
  448. +            HI3110_INT_RXFIFO | HI3110_INT_TXCPLT);
  449. +
  450. +   /* Enable TX */
  451. +   hi3110_write(spi, HI3110_WRITE_CTRL1, HI3110_CTRL1_TXEN);
  452. +
  453. +   if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
  454. +       reg = HI3110_CTRL0_LOOPBACK_MODE;
  455. +   else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
  456. +       reg = HI3110_CTRL0_MONITOR_MODE;
  457. +   else
  458. +       reg = HI3110_CTRL0_NORMAL_MODE;
  459. +
  460. +   hi3110_write(spi, HI3110_WRITE_CTRL0, reg);
  461. +
  462. +   /* Wait for the device to enter the mode */
  463. +   mdelay(HI3110_OST_DELAY_MS);
  464. +   reg = hi3110_read(spi, HI3110_READ_CTRL0);
  465. +   if ((reg & HI3110_CTRL0_MODE_MASK) != reg)
  466. +       return -EBUSY;
  467. +
  468. +   priv->can.state = CAN_STATE_ERROR_ACTIVE;
  469. +   return 0;
  470. +}
  471. +
  472. +static int hi3110_do_set_bittiming(struct net_device *net)
  473. +{
  474. +   struct hi3110_priv *priv = netdev_priv(net);
  475. +   struct can_bittiming *bt = &priv->can.bittiming;
  476. +   struct spi_device *spi = priv->spi;
  477. +
  478. +   hi3110_write(spi, HI3110_WRITE_BTR0,
  479. +            ((bt->sjw - 1) << HI3110_BTR0_SJW_SHIFT) |
  480. +            ((bt->brp - 1) << HI3110_BTR0_BRP_SHIFT));
  481. +
  482. +   hi3110_write(spi, HI3110_WRITE_BTR1,
  483. +            (priv->can.ctrlmode &
  484. +            CAN_CTRLMODE_3_SAMPLES ?
  485. +            HI3110_BTR1_SAMP_3PERBIT : HI3110_BTR1_SAMP_1PERBIT) |
  486. +            ((bt->phase_seg1 + bt->prop_seg - 1)
  487. +            << HI3110_BTR1_TSEG1_SHIFT) |
  488. +            ((bt->phase_seg2 - 1) << HI3110_BTR1_TSEG2_SHIFT));
  489. +
  490. +   dev_dbg(&spi->dev, "BT: 0x%02x 0x%02x\n",
  491. +       hi3110_read(spi, HI3110_READ_BTR0),
  492. +       hi3110_read(spi, HI3110_READ_BTR1));
  493. +
  494. +   return 0;
  495. +}
  496. +
  497. +static int hi3110_setup(struct net_device *net)
  498. +{
  499. +   hi3110_do_set_bittiming(net);
  500. +   return 0;
  501. +}
  502. +
  503. +static int hi3110_hw_reset(struct spi_device *spi)
  504. +{
  505. +   u8 reg;
  506. +   int ret;
  507. +
  508. +   /* Wait for oscillator startup timer after power up */
  509. +   mdelay(HI3110_OST_DELAY_MS);
  510. +
  511. +   ret = hi3110_cmd(spi, HI3110_MASTER_RESET);
  512. +   if (ret)
  513. +       return ret;
  514. +
  515. +   /* Wait for oscillator startup timer after reset */
  516. +   mdelay(HI3110_OST_DELAY_MS);
  517. +
  518. +   reg = hi3110_read(spi, HI3110_READ_CTRL0);
  519. +   if ((reg & HI3110_CTRL0_MODE_MASK) != HI3110_CTRL0_INIT_MODE)
  520. +       return -ENODEV;
  521. +
  522. +   /* As per the datasheet it appears the error flags are
  523. +    * not cleared on reset. Explicitly clear them by performing a read
  524. +    */
  525. +   hi3110_read(spi, HI3110_READ_ERR);
  526. +
  527. +   return 0;
  528. +}
  529. +
  530. +static int hi3110_hw_probe(struct spi_device *spi)
  531. +{
  532. +   u8 statf;
  533. +
  534. +   hi3110_hw_reset(spi);
  535. +
  536. +   /* Confirm correct operation by checking against reset values
  537. +    * in datasheet
  538. +    */
  539. +   statf = hi3110_read(spi, HI3110_READ_STATF);
  540. +
  541. +   dev_dbg(&spi->dev, "statf: %02X\n", statf);
  542. +
  543. +   if (statf != 0x82)
  544. +       return -ENODEV;
  545. +
  546. +   return 0;
  547. +}
  548. +
  549. +static int hi3110_power_enable(struct regulator *reg, int enable)
  550. +{
  551. +   if (IS_ERR_OR_NULL(reg))
  552. +       return 0;
  553. +
  554. +   if (enable)
  555. +       return regulator_enable(reg);
  556. +   else
  557. +       return regulator_disable(reg);
  558. +}
  559. +
  560. +static int hi3110_stop(struct net_device *net)
  561. +{
  562. +   struct hi3110_priv *priv = netdev_priv(net);
  563. +   struct spi_device *spi = priv->spi;
  564. +
  565. +   close_candev(net);
  566. +
  567. +   priv->force_quit = 1;
  568. +   free_irq(spi->irq, priv);
  569. +   destroy_workqueue(priv->wq);
  570. +   priv->wq = NULL;
  571. +
  572. +   mutex_lock(&priv->hi3110_lock);
  573. +
  574. +   /* Disable transmit, interrupts and clear flags */
  575. +   hi3110_write(spi, HI3110_WRITE_CTRL1, 0x0);
  576. +   hi3110_write(spi, HI3110_WRITE_INTE, 0x0);
  577. +   hi3110_read(spi, HI3110_READ_INTF);
  578. +
  579. +   hi3110_clean(net);
  580. +
  581. +   hi3110_hw_sleep(spi);
  582. +
  583. +   hi3110_power_enable(priv->transceiver, 0);
  584. +
  585. +   priv->can.state = CAN_STATE_STOPPED;
  586. +
  587. +   mutex_unlock(&priv->hi3110_lock);
  588. +
  589. +   can_led_event(net, CAN_LED_EVENT_STOP);
  590. +
  591. +   return 0;
  592. +}
  593. +
  594. +static void hi3110_tx_work_handler(struct work_struct *ws)
  595. +{
  596. +   struct hi3110_priv *priv = container_of(ws, struct hi3110_priv,
  597. +                        tx_work);
  598. +   struct spi_device *spi = priv->spi;
  599. +   struct net_device *net = priv->net;
  600. +   struct can_frame *frame;
  601. +
  602. +   mutex_lock(&priv->hi3110_lock);
  603. +   if (priv->tx_skb) {
  604. +       if (priv->can.state == CAN_STATE_BUS_OFF) {
  605. +           hi3110_clean(net);
  606. +       } else {
  607. +           frame = (struct can_frame *)priv->tx_skb->data;
  608. +           hi3110_hw_tx(spi, frame);
  609. +           priv->tx_len = 1 + frame->can_dlc;
  610. +           can_put_echo_skb(priv->tx_skb, net, 0);
  611. +           priv->tx_skb = NULL;
  612. +       }
  613. +   }
  614. +   mutex_unlock(&priv->hi3110_lock);
  615. +}
  616. +
  617. +static void hi3110_restart_work_handler(struct work_struct *ws)
  618. +{
  619. +   struct hi3110_priv *priv = container_of(ws, struct hi3110_priv,
  620. +                        restart_work);
  621. +   struct spi_device *spi = priv->spi;
  622. +   struct net_device *net = priv->net;
  623. +
  624. +   mutex_lock(&priv->hi3110_lock);
  625. +   if (priv->after_suspend) {
  626. +       hi3110_hw_reset(spi);
  627. +       hi3110_setup(net);
  628. +       if (priv->after_suspend & HI3110_AFTER_SUSPEND_RESTART) {
  629. +           hi3110_set_normal_mode(spi);
  630. +       } else if (priv->after_suspend & HI3110_AFTER_SUSPEND_UP) {
  631. +           netif_device_attach(net);
  632. +           hi3110_clean(net);
  633. +           hi3110_set_normal_mode(spi);
  634. +           netif_wake_queue(net);
  635. +       } else {
  636. +           hi3110_hw_sleep(spi);
  637. +       }
  638. +       priv->after_suspend = 0;
  639. +       priv->force_quit = 0;
  640. +   }
  641. +
  642. +   if (priv->restart_tx) {
  643. +       priv->restart_tx = 0;
  644. +       hi3110_hw_reset(spi);
  645. +       hi3110_setup(net);
  646. +       hi3110_clean(net);
  647. +       hi3110_set_normal_mode(spi);
  648. +       netif_wake_queue(net);
  649. +   }
  650. +   mutex_unlock(&priv->hi3110_lock);
  651. +}
  652. +
  653. +static irqreturn_t hi3110_can_ist(int irq, void *dev_id)
  654. +{
  655. +   struct hi3110_priv *priv = dev_id;
  656. +   struct spi_device *spi = priv->spi;
  657. +   struct net_device *net = priv->net;
  658. +
  659. +   mutex_lock(&priv->hi3110_lock);
  660. +
  661. +   while (!priv->force_quit) {
  662. +       enum can_state new_state;
  663. +       u8 intf, eflag, statf;
  664. +
  665. +       while (!(HI3110_STAT_RXFMTY &
  666. +              (statf = hi3110_read(spi, HI3110_READ_STATF)))) {
  667. +           hi3110_hw_rx(spi);
  668. +       }
  669. +
  670. +       intf = hi3110_read(spi, HI3110_READ_INTF);
  671. +       eflag = hi3110_read(spi, HI3110_READ_ERR);
  672. +       /* Update can state */
  673. +       if (eflag & HI3110_ERR_BUSOFF)
  674. +           new_state = CAN_STATE_BUS_OFF;
  675. +       else if (eflag & HI3110_ERR_PASSIVE_MASK)
  676. +           new_state = CAN_STATE_ERROR_PASSIVE;
  677. +       else if (statf & HI3110_STAT_ERRW)
  678. +           new_state = CAN_STATE_ERROR_WARNING;
  679. +       else
  680. +           new_state = CAN_STATE_ERROR_ACTIVE;
  681. +
  682. +       if (new_state != priv->can.state) {
  683. +           struct can_frame *cf;
  684. +           struct sk_buff *skb;
  685. +           enum can_state rx_state, tx_state;
  686. +           u8 rxerr, txerr;
  687. +
  688. +           skb = alloc_can_err_skb(net, &cf);
  689. +           if (!skb)
  690. +               break;
  691. +
  692. +           txerr = hi3110_read(spi, HI3110_READ_TEC);
  693. +           rxerr = hi3110_read(spi, HI3110_READ_REC);
  694. +           cf->data[6] = txerr;
  695. +           cf->data[7] = rxerr;
  696. +           tx_state = txerr >= rxerr ? new_state : 0;
  697. +           rx_state = txerr <= rxerr ? new_state : 0;
  698. +           can_change_state(net, cf, tx_state, rx_state);
  699. +           netif_rx_ni(skb);
  700. +
  701. +           if (new_state == CAN_STATE_BUS_OFF) {
  702. +               can_bus_off(net);
  703. +               if (priv->can.restart_ms == 0) {
  704. +                   priv->force_quit = 1;
  705. +                   hi3110_hw_sleep(spi);
  706. +                   break;
  707. +               }
  708. +           }
  709. +       }
  710. +
  711. +       /* Update bus errors */
  712. +       if ((intf & HI3110_INT_BUSERR) &&
  713. +           (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
  714. +           struct can_frame *cf;
  715. +           struct sk_buff *skb;
  716. +
  717. +           /* Check for protocol errors */
  718. +           if (eflag & HI3110_ERR_PROTOCOL_MASK) {
  719. +               skb = alloc_can_err_skb(net, &cf);
  720. +               if (!skb)
  721. +                   break;
  722. +
  723. +               cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
  724. +               priv->can.can_stats.bus_error++;
  725. +               priv->net->stats.rx_errors++;
  726. +               if (eflag & HI3110_ERR_BITERR)
  727. +                   cf->data[2] |= CAN_ERR_PROT_BIT;
  728. +               else if (eflag & HI3110_ERR_FRMERR)
  729. +                   cf->data[2] |= CAN_ERR_PROT_FORM;
  730. +               else if (eflag & HI3110_ERR_STUFERR)
  731. +                   cf->data[2] |= CAN_ERR_PROT_STUFF;
  732. +               else if (eflag & HI3110_ERR_CRCERR)
  733. +                   cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
  734. +               else if (eflag & HI3110_ERR_ACKERR)
  735. +                   cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
  736. +
  737. +               cf->data[6] = hi3110_read(spi, HI3110_READ_TEC);
  738. +               cf->data[7] = hi3110_read(spi, HI3110_READ_REC);
  739. +               netdev_dbg(priv->net, "Bus Error\n");
  740. +               netif_rx_ni(skb);
  741. +           }
  742. +       }
  743. +
  744. +       if (intf == 0)
  745. +           break;
  746. +
  747. +       if (intf & HI3110_INT_TXCPLT) {
  748. +           net->stats.tx_packets++;
  749. +           net->stats.tx_bytes += priv->tx_len - 1;
  750. +           can_led_event(net, CAN_LED_EVENT_TX);
  751. +           if (priv->tx_len) {
  752. +               can_get_echo_skb(net, 0);
  753. +               priv->tx_len = 0;
  754. +           }
  755. +           netif_wake_queue(net);
  756. +       }
  757. +   }
  758. +   mutex_unlock(&priv->hi3110_lock);
  759. +   return IRQ_HANDLED;
  760. +}
  761. +
  762. +static int hi3110_open(struct net_device *net)
  763. +{
  764. +   struct hi3110_priv *priv = netdev_priv(net);
  765. +   struct spi_device *spi = priv->spi;
  766. +   unsigned long flags = IRQF_ONESHOT | IRQF_TRIGGER_RISING;
  767. +   int ret;
  768. +
  769. +   ret = open_candev(net);
  770. +   if (ret)
  771. +       return ret;
  772. +
  773. +   mutex_lock(&priv->hi3110_lock);
  774. +   hi3110_power_enable(priv->transceiver, 1);
  775. +
  776. +   priv->force_quit = 0;
  777. +   priv->tx_skb = NULL;
  778. +   priv->tx_len = 0;
  779. +
  780. +   ret = request_threaded_irq(spi->irq, NULL, hi3110_can_ist,
  781. +                  flags, DEVICE_NAME, priv);
  782. +   if (ret) {
  783. +       dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq);
  784. +       goto out_close;
  785. +   }
  786. +
  787. +   priv->wq = alloc_workqueue("hi3110_wq", WQ_FREEZABLE | WQ_MEM_RECLAIM,
  788. +              0);
  789. +   INIT_WORK(&priv->tx_work, hi3110_tx_work_handler);
  790. +   INIT_WORK(&priv->restart_work, hi3110_restart_work_handler);
  791. +
  792. +   ret = hi3110_hw_reset(spi);
  793. +   if (ret)
  794. +       goto out_free_irq;
  795. +
  796. +   ret = hi3110_setup(net);
  797. +   if (ret)
  798. +       goto out_free_irq;
  799. +
  800. +   ret = hi3110_set_normal_mode(spi);
  801. +   if (ret)
  802. +       goto out_free_irq;
  803. +
  804. +   can_led_event(net, CAN_LED_EVENT_OPEN);
  805. +   netif_wake_queue(net);
  806. +   mutex_unlock(&priv->hi3110_lock);
  807. +
  808. +   return 0;
  809. +
  810. +out_free_irq:
  811. +   free_irq(spi->irq, priv);
  812. +   hi3110_hw_sleep(spi);
  813. +
  814. +out_close:
  815. +   hi3110_power_enable(priv->transceiver, 0);
  816. +   close_candev(net);
  817. +   mutex_unlock(&priv->hi3110_lock);
  818. +   return ret;
  819. +}
  820. +
  821. +static const struct net_device_ops hi3110_netdev_ops = {
  822. +   .ndo_open = hi3110_open,
  823. +   .ndo_stop = hi3110_stop,
  824. +   .ndo_start_xmit = hi3110_hard_start_xmit,
  825. +};
  826. +
  827. +static const struct of_device_id hi3110_of_match[] = {
  828. +   {
  829. +       .compatible = "holt,hi3110",
  830. +       .data       = (void *)CAN_HI3110_HI3110,
  831. +   },
  832. +   { }
  833. +};
  834. +MODULE_DEVICE_TABLE(of, hi3110_of_match);
  835. +
  836. +static const struct spi_device_id hi3110_id_table[] = {
  837. +   {
  838. +       .name       = "hi3110",
  839. +       .driver_data    = (kernel_ulong_t)CAN_HI3110_HI3110,
  840. +   },
  841. +   { }
  842. +};
  843. +MODULE_DEVICE_TABLE(spi, hi3110_id_table);
  844. +
  845. +static int hi3110_can_probe(struct spi_device *spi)
  846. +{
  847. +   const struct of_device_id *of_id = of_match_device(hi3110_of_match,
  848. +                              &spi->dev);
  849. +   struct net_device *net;
  850. +   struct hi3110_priv *priv;
  851. +   struct clk *clk;
  852. +   int freq, ret;
  853. +
  854. +   clk = devm_clk_get(&spi->dev, NULL);
  855. +   if (IS_ERR(clk)) {
  856. +       dev_err(&spi->dev, "no CAN clock source defined\n");
  857. +       return PTR_ERR(clk);
  858. +   }
  859. +   freq = clk_get_rate(clk);
  860. +
  861. +   /* Sanity check */
  862. +   if (freq > 40000000)
  863. +       return -ERANGE;
  864. +
  865. +   /* Allocate can/net device */
  866. +   net = alloc_candev(sizeof(struct hi3110_priv), HI3110_TX_ECHO_SKB_MAX);
  867. +   if (!net)
  868. +       return -ENOMEM;
  869. +
  870. +   if (!IS_ERR(clk)) {
  871. +       ret = clk_prepare_enable(clk);
  872. +       if (ret)
  873. +           goto out_free;
  874. +   }
  875. +
  876. +   net->netdev_ops = &hi3110_netdev_ops;
  877. +   net->flags |= IFF_ECHO;
  878. +
  879. +   priv = netdev_priv(net);
  880. +   priv->can.bittiming_const = &hi3110_bittiming_const;
  881. +   priv->can.do_set_mode = hi3110_do_set_mode;
  882. +   priv->can.do_get_berr_counter = hi3110_get_berr_counter;
  883. +   priv->can.clock.freq = freq / 2;
  884. +   priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
  885. +                      CAN_CTRLMODE_LOOPBACK |
  886. +                      CAN_CTRLMODE_LISTENONLY |
  887. +                      CAN_CTRLMODE_BERR_REPORTING;
  888. +
  889. +   if (of_id)
  890. +       priv->model = (enum hi3110_model)of_id->data;
  891. +   else
  892. +       priv->model = spi_get_device_id(spi)->driver_data;
  893. +   priv->net = net;
  894. +   priv->clk = clk;
  895. +
  896. +   spi_set_drvdata(spi, priv);
  897. +
  898. +   /* Configure the SPI bus */
  899. +   spi->bits_per_word = 8;
  900. +   ret = spi_setup(spi);
  901. +   if (ret)
  902. +       goto out_clk;
  903. +
  904. +   priv->power = devm_regulator_get_optional(&spi->dev, "vdd");
  905. +   priv->transceiver = devm_regulator_get_optional(&spi->dev, "xceiver");
  906. +   if ((PTR_ERR(priv->power) == -EPROBE_DEFER) ||
  907. +       (PTR_ERR(priv->transceiver) == -EPROBE_DEFER)) {
  908. +       ret = -EPROBE_DEFER;
  909. +       goto out_clk;
  910. +   }
  911. +
  912. +   ret = hi3110_power_enable(priv->power, 1);
  913. +   if (ret)
  914. +       goto out_clk;
  915. +
  916. +   priv->spi = spi;
  917. +   mutex_init(&priv->hi3110_lock);
  918. +
  919. +   /* If requested, allocate DMA buffers */
  920. +   if (hi3110_enable_dma) {
  921. +       spi->dev.coherent_dma_mask = ~0;
  922. +
  923. +       /* Minimum coherent DMA allocation is PAGE_SIZE, so allocate
  924. +        * that much and share it between Tx and Rx DMA buffers.
  925. +        */
  926. +       priv->spi_tx_buf = dmam_alloc_coherent(&spi->dev,
  927. +                             PAGE_SIZE,
  928. +                             &priv->spi_tx_dma,
  929. +                             GFP_DMA);
  930. +
  931. +       if (priv->spi_tx_buf) {
  932. +           priv->spi_rx_buf = (priv->spi_tx_buf + (PAGE_SIZE / 2));
  933. +           priv->spi_rx_dma = (dma_addr_t)(priv->spi_tx_dma +
  934. +                           (PAGE_SIZE / 2));
  935. +       } else {
  936. +           /* Fall back to non-DMA */
  937. +           hi3110_enable_dma = 0;
  938. +       }
  939. +   }
  940. +
  941. +   /* Allocate non-DMA buffers */
  942. +   if (!hi3110_enable_dma) {
  943. +       priv->spi_tx_buf = devm_kzalloc(&spi->dev, HI3110_RX_BUF_LEN,
  944. +               GFP_KERNEL);
  945. +       if (!priv->spi_tx_buf) {
  946. +           ret = -ENOMEM;
  947. +           goto error_probe;
  948. +       }
  949. +       priv->spi_rx_buf = devm_kzalloc(&spi->dev, HI3110_RX_BUF_LEN,
  950. +               GFP_KERNEL);
  951. +
  952. +       if (!priv->spi_rx_buf) {
  953. +           ret = -ENOMEM;
  954. +           goto error_probe;
  955. +       }
  956. +   }
  957. +
  958. +   SET_NETDEV_DEV(net, &spi->dev);
  959. +
  960. +   ret = hi3110_hw_probe(spi);
  961. +   if (ret) {
  962. +       if (ret == -ENODEV)
  963. +           dev_err(&spi->dev, "Cannot initialize %x. Wrong wiring?\n",
  964. +               priv->model);
  965. +       goto error_probe;
  966. +   }
  967. +   hi3110_hw_sleep(spi);
  968. +
  969. +   ret = register_candev(net);
  970. +   if (ret)
  971. +       goto error_probe;
  972. +
  973. +   devm_can_led_init(net);
  974. +   netdev_info(net, "%x successfully initialized.\n", priv->model);
  975. +
  976. +   return 0;
  977. +
  978. +error_probe:
  979. +   hi3110_power_enable(priv->power, 0);
  980. +
  981. +out_clk:
  982. +   if (!IS_ERR(clk))
  983. +       clk_disable_unprepare(clk);
  984. +
  985. +out_free:
  986. +   free_candev(net);
  987. +
  988. +   dev_err(&spi->dev, "Probe failed, err=%d\n", -ret);
  989. +   return ret;
  990. +}
  991. +
  992. +static int hi3110_can_remove(struct spi_device *spi)
  993. +{
  994. +   struct hi3110_priv *priv = spi_get_drvdata(spi);
  995. +   struct net_device *net = priv->net;
  996. +
  997. +   unregister_candev(net);
  998. +
  999. +   hi3110_power_enable(priv->power, 0);
  1000. +
  1001. +   if (!IS_ERR(priv->clk))
  1002. +       clk_disable_unprepare(priv->clk);
  1003. +
  1004. +   free_candev(net);
  1005. +
  1006. +   return 0;
  1007. +}
  1008. +
  1009. +static int __maybe_unused hi3110_can_suspend(struct device *dev)
  1010. +{
  1011. +   struct spi_device *spi = to_spi_device(dev);
  1012. +   struct hi3110_priv *priv = spi_get_drvdata(spi);
  1013. +   struct net_device *net = priv->net;
  1014. +
  1015. +   priv->force_quit = 1;
  1016. +   disable_irq(spi->irq);
  1017. +
  1018. +   /* Note: at this point neither IST nor workqueues are running.
  1019. +    * open/stop cannot be called anyway so locking is not needed
  1020. +    */
  1021. +   if (netif_running(net)) {
  1022. +       netif_device_detach(net);
  1023. +
  1024. +       hi3110_hw_sleep(spi);
  1025. +       hi3110_power_enable(priv->transceiver, 0);
  1026. +       priv->after_suspend = HI3110_AFTER_SUSPEND_UP;
  1027. +   } else {
  1028. +       priv->after_suspend = HI3110_AFTER_SUSPEND_DOWN;
  1029. +   }
  1030. +
  1031. +   if (!IS_ERR_OR_NULL(priv->power)) {
  1032. +       regulator_disable(priv->power);
  1033. +       priv->after_suspend |= HI3110_AFTER_SUSPEND_POWER;
  1034. +   }
  1035. +
  1036. +   return 0;
  1037. +}
  1038. +
  1039. +static int __maybe_unused hi3110_can_resume(struct device *dev)
  1040. +{
  1041. +   struct spi_device *spi = to_spi_device(dev);
  1042. +   struct hi3110_priv *priv = spi_get_drvdata(spi);
  1043. +
  1044. +   if (priv->after_suspend & HI3110_AFTER_SUSPEND_POWER)
  1045. +       hi3110_power_enable(priv->power, 1);
  1046. +
  1047. +   if (priv->after_suspend & HI3110_AFTER_SUSPEND_UP) {
  1048. +       hi3110_power_enable(priv->transceiver, 1);
  1049. +       queue_work(priv->wq, &priv->restart_work);
  1050. +   } else {
  1051. +       priv->after_suspend = 0;
  1052. +   }
  1053. +
  1054. +   priv->force_quit = 0;
  1055. +   enable_irq(spi->irq);
  1056. +   return 0;
  1057. +}
  1058. +
  1059. +static SIMPLE_DEV_PM_OPS(hi3110_can_pm_ops, hi3110_can_suspend,
  1060. +   hi3110_can_resume);
  1061. +
  1062. +static struct spi_driver hi3110_can_driver = {
  1063. +   .driver = {
  1064. +       .name = DEVICE_NAME,
  1065. +       .of_match_table = hi3110_of_match,
  1066. +       .pm = &hi3110_can_pm_ops,
  1067. +   },
  1068. +   .id_table = hi3110_id_table,
  1069. +   .probe = hi3110_can_probe,
  1070. +   .remove = hi3110_can_remove,
  1071. +};
  1072. +
  1073. +module_spi_driver(hi3110_can_driver);
  1074. +
  1075. +MODULE_AUTHOR("Akshay Bhat <akshay.bhat@timesys.com>");
  1076. +MODULE_AUTHOR("Casey Fitzpatrick <casey.fitzpatrick@timesys.com>");
  1077. +MODULE_DESCRIPTION("Holt HI-3110 CAN driver");
  1078. +MODULE_LICENSE("GPL v2");
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