SW[0] - select
SW[1] - input 1
SW[2] - input 2
LEDR[0] - output

module ligths (SW[0], SW[1], SW[2], LEDR[0]);

input SW[0], SW[1], SW[2];

output LEDR[0];

assign LEDR[0] = ((SW[2] & SW[0]) | (SW[1] & ~SW[0]));

endmodule