Ring Oscillator in VHDL

    -- Resettable Ring Oscillator
    -- by Michael Frank (FAMU/FSU), 4/11/2011
    -- (released to public domain)

    -- NOTE: The precise clock frequency will vary depending on placement
    -- and routing, manufacturing variation, temperature, etc., so cannot
    -- be relied upon unless ALL of these factors are controlled.
    -- I measured speeds of up to 666 MHz with this code on an Altera DE2
    -- board (Cyclone II EP2C35F672C6N FPGA) without controlling placement.

library ieee;
    use ieee.std_logic_1164.all;

entity ring_osc is
    port (
        reset_n: in std_logic;  -- active-low asynchronous reset
        clk_out: out std_logic  -- synthesized clock
    );
end entity;

architecture structure of ring_osc is
    signal node: std_logic_vector(1 to 3);      -- Internal nodes.

        -- The following is essential to prevent the circuit from
        -- being simplified to a single NAND, which may not work,
        -- since it can settle into a stable short-circuit state
        -- with an output value between 0 and 1.  (Also, even if
        -- it worked it would prob. be too fast to use the ring
        -- osc. to drive any sequential logic).

    attribute keep: boolean;
    attribute keep of node: signal is true;
begin
        -- Here is the ring oscillator itself.
        -- Note that we have to specify the keep attribute for
        -- all of these nodes to keep the NOTs from being optimized away.

    node(1) <= node(3) nand reset_n;
    node(2) <= not node(1);
    node(3) <= not node(2);

        -- We tap out of it with an inverter to keep the frequency
        -- independent of the load.

    clk_out <= not node(1);

end architecture;