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  1. /*
  2. * Copyright 2013 CompuLab Ltd.
  3. *
  4. * Author: Valentin Raevsky <valentin@compulab.co.il>
  5. *
  6. * The code contained herein is licensed under the GNU General Public
  7. * License. You may obtain a copy of the GNU General Public License
  8. * Version 2 or later at the following locations:
  9. *
  10. * http://www.opensource.org/licenses/gpl-license.html
  11. * http://www.gnu.org/copyleft/gpl.html
  12. */
  13.  
  14. /dts-v1/;
  15. #include "imx6q.dtsi"
  16.  
  17. / {
  18. model = "CompuLab CM-FX6";
  19. compatible = "compulab,cm-fx6", "fsl,imx6q";
  20.  
  21. memory {
  22. reg = <0x10000000 0x80000000>;
  23. };
  24.  
  25. leds {
  26. compatible = "gpio-leds";
  27.  
  28. heartbeat-led {
  29. label = "Heartbeat";
  30. gpios = <&gpio2 31 0>;
  31. linux,default-trigger = "heartbeat";
  32. };
  33. };
  34.  
  35. soc {
  36.  
  37.  
  38. hdmi_core: hdmi_core@00120000 {
  39. compatible = "fsl,imx6q-hdmi-core";
  40. reg = <0x00120000 0x9000>;
  41. clocks = <&clks 124>, <&clks 123>;
  42. clock-names = "hdmi_isfr", "hdmi_iahb";
  43. status = "disabled";
  44. };
  45.  
  46. hdmi_video: hdmi_video@020e0000 {
  47. compatible = "fsl,imx6q-hdmi-video";
  48. reg = <0x020e0000 0x1000>;
  49. reg-names = "hdmi_gpr";
  50. interrupts = <0 115 0x04>;
  51. clocks = <&clks 124>, <&clks 123>;
  52. clock-names = "hdmi_isfr", "hdmi_iahb";
  53. status = "disabled";
  54. };
  55.  
  56. hdmi_audio: hdmi_audio@00120000 {
  57. compatible = "fsl,imx6q-hdmi-audio";
  58. clocks = <&clks 124>, <&clks 123>;
  59. clock-names = "hdmi_isfr", "hdmi_iahb";
  60. dmas = <&sdma 2 22 0>;
  61. dma-names = "tx";
  62. status = "disabled";
  63. };
  64.  
  65. };
  66.  
  67. regulators {
  68. compatible = "simple-bus";
  69. #address-cells = <1>;
  70. #size-cells = <0>;
  71.  
  72. /* regulator for mmc */
  73. reg_3p3v: 3p3v {
  74. compatible = "regulator-fixed";
  75. regulator-name = "3P3V";
  76. regulator-min-microvolt = <3300000>;
  77. regulator-max-microvolt = <3300000>;
  78. regulator-always-on;
  79. };
  80.  
  81. /* regulator for usb otg */
  82. reg_usb_otg_vbus: usb_otg_vbus {
  83. compatible = "regulator-fixed";
  84. regulator-name = "usb_otg_vbus";
  85. regulator-min-microvolt = <5000000>;
  86. regulator-max-microvolt = <5000000>;
  87. gpio = <&gpio3 22 0>;
  88. enable-active-high;
  89. };
  90.  
  91. /* regulator for usb hub1 */
  92. reg_usb_h1_vbus: usb_h1_vbus {
  93. compatible = "regulator-fixed";
  94. regulator-name = "usb_h1_vbus";
  95. regulator-min-microvolt = <5000000>;
  96. regulator-max-microvolt = <5000000>;
  97. gpio = <&gpio7 8 0>;
  98. enable-active-high;
  99. };
  100.  
  101. /* regulator1 for wifi/bt */
  102. awnh387_npoweron: regulator-awnh387-npoweron {
  103. compatible = "regulator-fixed";
  104. regulator-name = "regulator-awnh387-npoweron";
  105. regulator-min-microvolt = <3300000>;
  106. regulator-max-microvolt = <3300000>;
  107. gpio = <&gpio7 12 0>;
  108. enable-active-high;
  109. };
  110.  
  111. /* regulator2 for wifi/bt */
  112. awnh387_wifi_nreset: regulator-awnh387-wifi-nreset {
  113. compatible = "regulator-fixed";
  114. regulator-name = "regulator-awnh387-wifi-nreset";
  115. regulator-min-microvolt = <3300000>;
  116. regulator-max-microvolt = <3300000>;
  117. gpio = <&gpio6 16 0>;
  118. startup-delay-us = <10000>;
  119. };
  120.  
  121. reg_sata_phy_slp: sata_phy_slp {
  122. compatible = "regulator-fixed";
  123. regulator-name = "cm_fx6_sata_phy_slp";
  124. regulator-min-microvolt = <3300000>;
  125. regulator-max-microvolt = <3300000>;
  126. gpio = <&gpio3 23 0>;
  127. startup-delay-us = <100>;
  128. enable-active-high;
  129. };
  130.  
  131. reg_sata_nrstdly: sata_nrstdly {
  132. compatible = "regulator-fixed";
  133. regulator-name = "cm_fx6_sata_nrstdly";
  134. regulator-min-microvolt = <3300000>;
  135. regulator-max-microvolt = <3300000>;
  136. gpio = <&gpio6 6 0>;
  137. startup-delay-us = <100>;
  138. enable-active-high;
  139. vin-supply = <&reg_sata_phy_slp>;
  140. };
  141.  
  142. reg_sata_pwren: sata_pwren {
  143. compatible = "regulator-fixed";
  144. regulator-name = "cm_fx6_sata_pwren";
  145. regulator-min-microvolt = <3300000>;
  146. regulator-max-microvolt = <3300000>;
  147. gpio = <&gpio1 28 0>;
  148. startup-delay-us = <100>;
  149. enable-active-high;
  150. vin-supply = <&reg_sata_nrstdly>;
  151. };
  152.  
  153. reg_sata_nstandby1: sata_nstandby1 {
  154. compatible = "regulator-fixed";
  155. regulator-name = "cm_fx6_sata_nstandby1";
  156. regulator-min-microvolt = <3300000>;
  157. regulator-max-microvolt = <3300000>;
  158. gpio = <&gpio3 20 0>;
  159. startup-delay-us = <100>;
  160. enable-active-high;
  161. vin-supply = <&reg_sata_pwren>;
  162. };
  163.  
  164. reg_sata_nstandby2: sata_nstandby2 {
  165. compatible = "regulator-fixed";
  166. regulator-name = "cm_fx6_sata_nstandby2";
  167. regulator-min-microvolt = <3300000>;
  168. regulator-max-microvolt = <3300000>;
  169. gpio = <&gpio5 2 0>;
  170. startup-delay-us = <100>;
  171. enable-active-high;
  172. vin-supply = <&reg_sata_nstandby1>;
  173. };
  174.  
  175. reg_sata_ldo_en: sata_ldo_en {
  176. compatible = "regulator-fixed";
  177. regulator-name = "cm_fx6_sata_ldo_en";
  178. regulator-min-microvolt = <3300000>;
  179. regulator-max-microvolt = <3300000>;
  180. gpio = <&gpio2 16 0>;
  181. startup-delay-us = <100>;
  182. enable-active-high;
  183. regulator-boot-on;
  184. vin-supply = <&reg_sata_nstandby2>;
  185. };
  186. };
  187.  
  188. gpio-keys {
  189. compatible = "gpio-keys";
  190. power {
  191. label = "Power Button";
  192. gpios = <&gpio1 29 1>;
  193. linux,code = <116>; /* KEY_POWER */
  194. gpio-key,wakeup;
  195. };
  196. };
  197.  
  198. aliases {
  199. mxcfb0 = &mxcfb1;
  200. mxcfb1 = &mxcfb2;
  201. };
  202.  
  203. sound {
  204. compatible = "fsl,imx6q-cm-fx6-wm8731",
  205. "fsl,imx-audio-wm8731";
  206. model = "wm8731-audio";
  207. ssi-controller = <&ssi2>;
  208. src-port = <2>;
  209. ext-port = <4>;
  210. audio-codec = <&codec>;
  211. audio-routing = "LOUT", "ROUT", "LLINEIN", "RLINEIN";
  212. };
  213.  
  214. sound-hdmi {
  215. compatible = "fsl,imx6q-audio-hdmi",
  216. "fsl,imx-audio-hdmi";
  217. model = "imx-audio-hdmi";
  218. hdmi-controller = <&hdmi_audio>;
  219. };
  220.  
  221. sound-spdif {
  222. compatible = "fsl,imx-audio-spdif",
  223. "fsl,imx-sabreauto-spdif";
  224. model = "imx-spdif";
  225. spdif-controller = <&spdif>;
  226. spdif-out;
  227. spdif-in;
  228. };
  229.  
  230. mxcfb1: fb@0 {
  231. compatible = "fsl,mxc_sdc_fb";
  232. disp_dev = "hdmi";
  233. interface_pix_fmt = "RGB24";
  234. mode_str ="1920x1080M@60";
  235. default_bpp = <32>;
  236. int_clk = <0>;
  237. late_init = <0>;
  238. status = "disabled";
  239. };
  240.  
  241. mxcfb2: fb@1 {
  242. compatible = "fsl,mxc_sdc_fb";
  243. disp_dev = "lcd";
  244. interface_pix_fmt = "RGB24";
  245. mode_str ="1920x1080M@60";
  246. default_bpp = <32>;
  247. int_clk = <0>;
  248. late_init = <0>;
  249. status = "disabled";
  250. };
  251.  
  252.  
  253. lcd@0 {
  254. compatible = "fsl,lcd";
  255. ipu_id = <0>;
  256. disp_id = <0>;
  257. default_ifmt = "RGB24";
  258. pinctrl-names = "default";
  259. pinctrl-0 = <&pinctrl_ipu1_1>;
  260. status = "okay";
  261. };
  262.  
  263. v4l2_out {
  264. compatible = "fsl,mxc_v4l2_output";
  265. status = "okay";
  266. };
  267.  
  268. eth@pcie {
  269. compatible = "intel,i211";
  270. local-mac-address = [00 1C 1D 1E 1F 20];
  271. status = "okay";
  272. };
  273.  
  274. };
  275.  
  276. &iomuxc {
  277. pinctrl-names = "default";
  278. pinctrl-0 = <&pinctrl_hog>;
  279.  
  280. hdmi_hdcp {
  281. pinctrl_hdmi_hdcp_1: hdmihdcpgrp-1 {
  282. fsl,pins = <
  283. MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
  284. MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
  285. >;
  286. };
  287.  
  288. pinctrl_hdmi_hdcp_2: hdmihdcpgrp-2 {
  289. fsl,pins = <
  290. MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
  291. MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
  292. >;
  293. };
  294.  
  295. pinctrl_hdmi_hdcp_3: hdmihdcpgrp-3 {
  296. fsl,pins = <
  297. MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
  298. MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
  299. >;
  300. };
  301. };
  302.  
  303.  
  304. ipu2 {
  305. pinctrl_ipu2_1: ipu2grp-1 {
  306. fsl,pins = <
  307. MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x10
  308. MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x10
  309. MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x10
  310. MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x10
  311. MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x80000000
  312. MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x10
  313. MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x10
  314. MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x10
  315. MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x10
  316. MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x10
  317. MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x10
  318. MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x10
  319. MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x10
  320. MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x10
  321. MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x10
  322. MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x10
  323. MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x10
  324. MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x10
  325. MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x10
  326. MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x10
  327. MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x10
  328. MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x10
  329. MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x10
  330. MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x10
  331. MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x10
  332. MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x10
  333. MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x10
  334. MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x10
  335. MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x10
  336. >;
  337. };
  338. };
  339.  
  340. ipu1 {
  341. pinctrl_ipu1_1: ipu1grp-1 {
  342. fsl,pins = <
  343. MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
  344. MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
  345. MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
  346. MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
  347. MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000
  348. MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
  349. MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
  350. MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
  351. MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
  352. MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
  353. MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
  354. MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
  355. MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
  356. MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
  357. MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
  358. MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
  359. MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
  360. MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
  361. MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
  362. MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
  363. MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
  364. MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
  365. MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
  366. MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
  367. MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
  368. MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
  369. MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
  370. MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
  371. MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
  372. >;
  373. };
  374.  
  375. pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */
  376. fsl,pins = <
  377. MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
  378. MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
  379. MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
  380. MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
  381. MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
  382. MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
  383. MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
  384. MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
  385. MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000
  386. MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
  387. MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
  388. MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
  389. >;
  390. };
  391.  
  392. pinctrl_ipu1_3: ipu1grp-3 { /* parallel port 16-bit */
  393. fsl,pins = <
  394. MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000
  395. MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000
  396. MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000
  397. MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000
  398. MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000
  399. MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000
  400. MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000
  401. MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000
  402. MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
  403. MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
  404. MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
  405. MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
  406. MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
  407. MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
  408. MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
  409. MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
  410. MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
  411. MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
  412. MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
  413. >;
  414. };
  415. };
  416.  
  417. hog {
  418. pinctrl_hog: hoggrp {
  419. fsl,pins = <
  420. /* SATA PWR */
  421. MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000
  422. MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x80000000
  423. MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x80000000
  424. MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000
  425. /* SATA CTRL */
  426. MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000
  427. MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000
  428. MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x80000000
  429. MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
  430. >;
  431. };
  432. };
  433.  
  434. imx6q-cm-fx6 {
  435. /* pins for eth0 */
  436. pinctrl_enet: enetgrp {
  437. fsl,pins = <
  438. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
  439. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
  440. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
  441. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
  442. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
  443. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
  444. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
  445. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
  446. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
  447. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
  448. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
  449. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
  450. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
  451. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  452. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  453. >;
  454. };
  455.  
  456. /* pins for spi */
  457. pinctrl_ecspi1: ecspi1grp {
  458. fsl,pins = <
  459. MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
  460. MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
  461. MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
  462. MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x100b1
  463. MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x100b1
  464. >;
  465. };
  466.  
  467. /* pins for nand */
  468. pinctrl_gpmi_nand: gpminandgrp {
  469. fsl,pins = <
  470. MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
  471. MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
  472. MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
  473. MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
  474. MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
  475. MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
  476. MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
  477. MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
  478. MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
  479. MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
  480. MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
  481. MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
  482. MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
  483. MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
  484. MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
  485. MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
  486. MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
  487. >;
  488. };
  489.  
  490. /* pins for i2c1 */
  491. pinctrl_i2c1: i2c1grp {
  492. fsl,pins = <
  493. MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
  494. MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
  495. >;
  496. };
  497.  
  498. /* pins for i2c2 */
  499. pinctrl_i2c2: i2c2grp {
  500. fsl,pins = <
  501. MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  502. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  503. >;
  504. };
  505.  
  506. /* pins for i2c3 */
  507. pinctrl_i2c3: i2c3grp {
  508. fsl,pins = <
  509. MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
  510. MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
  511. >;
  512. };
  513.  
  514. /* pins for console */
  515. pinctrl_uart4: uart4grp {
  516. fsl,pins = <
  517. MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
  518. MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
  519. >;
  520. };
  521.  
  522. /* pins for usb hub1 */
  523. pinctrl_usbh1: usbh1grp {
  524. fsl,pins = <
  525. MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x80000000
  526. >;
  527. };
  528.  
  529. /* pins for usb otg */
  530. pinctrl_usbotg: usbotggrp {
  531. fsl,pins = <
  532. MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
  533. MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
  534. >;
  535. };
  536.  
  537. /* pins for wifi/bt */
  538. pinctrl_usdhc1: usdhc1grp {
  539. fsl,pins = <
  540. MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
  541. MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
  542. MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
  543. MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
  544. MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
  545. MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
  546. >;
  547. };
  548.  
  549. /* pins for mmc */
  550. pinctrl_usdhc3: usdhc3grp {
  551. fsl,pins = <
  552. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
  553. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
  554. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  555. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  556. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  557. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  558. >;
  559. };
  560.  
  561. /* pins for spdif */
  562. pinctrl_spdif: spdifgrp {
  563. fsl,pins = <
  564. MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0
  565. MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0
  566. >;
  567. };
  568.  
  569. /* pins for audmux */
  570. pinctrl_audmux: audmuxgrp {
  571. fsl,pins = <
  572. MX6QDL_PAD_SD2_CMD__AUD4_RXC 0x17059
  573. MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x17059
  574. MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x17059
  575. MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x17059
  576. MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x17059
  577. /* master mode pin */
  578. MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x17059
  579. >;
  580. };
  581.  
  582. /* pins for uart2 */
  583. pinctrl_uart2: uart2grp {
  584. fsl,pins = <
  585. MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b0b1
  586. MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b0b1
  587. MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
  588. MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
  589. >;
  590. };
  591.  
  592. /* pins for pcie */
  593. pinctrl_pcie: pciegrp {
  594. fsl,pins = <
  595. MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000
  596. MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000
  597. >;
  598. };
  599. };
  600. };
  601.  
  602. /* spi */
  603. &ecspi1 {
  604. fsl,spi-num-chipselects = <2>;
  605. cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
  606. pinctrl-names = "default";
  607. pinctrl-0 = <&pinctrl_ecspi1>;
  608. status = "okay";
  609.  
  610. flash: m25p80@0 {
  611. #address-cells = <1>;
  612. #size-cells = <1>;
  613. compatible = "st,m25px16", "st,m25p";
  614. spi-max-frequency = <20000000>;
  615. reg = <0>;
  616.  
  617. partition@0 {
  618. label = "uboot";
  619. reg = <0x0 0xc0000>;
  620. };
  621.  
  622. partition@c0000 {
  623. label = "uboot environment";
  624. reg = <0xc0000 0x40000>;
  625. };
  626.  
  627. partition@100000 {
  628. label = "reserved";
  629. reg = <0x100000 0x100000>;
  630. };
  631. };
  632. };
  633.  
  634. /* eth0 */
  635. &fec {
  636. pinctrl-names = "default";
  637. pinctrl-0 = <&pinctrl_enet>;
  638. phy-mode = "rgmii";
  639. status = "okay";
  640. };
  641.  
  642. /* nand */
  643. &gpmi {
  644. pinctrl-names = "default";
  645. pinctrl-0 = <&pinctrl_gpmi_nand>;
  646. status = "okay";
  647. };
  648.  
  649. /* i2c1 */
  650. &i2c1 {
  651. pinctrl-names = "default";
  652. pinctrl-0 = <&pinctrl_i2c1>;
  653. status = "okay";
  654.  
  655. eeprom@50 {
  656. compatible = "at24,24c02";
  657. reg = <0x50>;
  658. pagesize = <16>;
  659. };
  660.  
  661. rtc@56 {
  662. compatible = "emmicro,em3027";
  663. reg = <0x56>;
  664. };
  665. };
  666.  
  667. /* i2c2 */
  668. &i2c2 {
  669. pinctrl-names = "default";
  670. pinctrl-0 = <&pinctrl_i2c2>;
  671. /* status = "okay"; */
  672. };
  673.  
  674. /* i2c3 */
  675. &i2c3 {
  676. pinctrl-names = "default";
  677. pinctrl-0 = <&pinctrl_i2c3>;
  678. status = "okay";
  679.  
  680. eeprom@50 {
  681. compatible = "at24,24c02";
  682. reg = <0x50>;
  683. pagesize = <16>;
  684. };
  685.  
  686. codec: wm8731@1a {
  687. compatible = "wlf,wm8731";
  688. reg = <0x1a>;
  689. clocks = <&clks 173>, <&clks 158>, <&clks 201>, <&clks 200>;
  690. clock-names = "pll4", "imx-ssi.1", "cko", "cko2";
  691. AVDD-supply = <&reg_3p3v>;
  692. HPVDD-supply = <&reg_3p3v>;
  693. DCVDD-supply = <&reg_3p3v>;
  694. DBVDD-supply = <&reg_3p3v>;
  695. };
  696. };
  697.  
  698. /* eth1 */
  699. &pcie {
  700. pinctrl-names = "default";
  701. pinctrl-0 = <&pinctrl_pcie>;
  702. reset-gpio = <&gpio1 26 0>;
  703. power-on-gpio = <&gpio2 24 0>;
  704. status = "okay";
  705. };
  706.  
  707. /* sata */
  708. &sata {
  709. status = "okay";
  710. };
  711.  
  712. /* rear serial console */
  713. &uart2 {
  714. pinctrl-names = "default";
  715. pinctrl-0 = <&pinctrl_uart2>;
  716. /* fsl,dte-mode; */
  717. fsl,uart-has-rtscts;
  718. dma-names = "rx", "tx";
  719. dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
  720. status = "okay";
  721. };
  722.  
  723. /* console */
  724. &uart4 {
  725. pinctrl-names = "default";
  726. pinctrl-0 = <&pinctrl_uart4>;
  727. status = "okay";
  728. };
  729.  
  730. /* usb otg */
  731. &usbotg {
  732. vbus-supply = <&reg_usb_otg_vbus>;
  733. pinctrl-names = "default";
  734. pinctrl-0 = <&pinctrl_usbotg>;
  735. dr_mode = "otg";
  736. status = "okay";
  737. };
  738.  
  739. /* usb hub1 */
  740. &usbh1 {
  741. vbus-supply = <&reg_usb_h1_vbus>;
  742. pinctrl-names = "default";
  743. pinctrl-0 = <&pinctrl_usbh1>;
  744. status = "okay";
  745. };
  746.  
  747. /* wifi/bt */
  748. &usdhc1 {
  749. pinctrl-names = "default";
  750. pinctrl-0 = <&pinctrl_usdhc1>;
  751. non-removable;
  752. vmmc-supply = <&awnh387_npoweron>;
  753. vmmc_aux-supply = <&awnh387_wifi_nreset>;
  754. status = "okay";
  755. };
  756.  
  757. /* mmc */
  758. &usdhc3 {
  759. pinctrl-names = "default";
  760. pinctrl-0 = <&pinctrl_usdhc3>;
  761. vmmc-supply = <&reg_3p3v>;
  762. status = "okay";
  763. };
  764.  
  765. &ssi2 {
  766. fsl,mode = "i2s-master";
  767. status = "okay";
  768. };
  769.  
  770. &mxcfb1 {
  771. status = "okay";
  772. };
  773.  
  774. &mxcfb2 {
  775. status = "okay";
  776. };
  777.  
  778. &hdmi_core {
  779. ipu_id = <1>;
  780. disp_id = <0>;
  781. status = "okay";
  782. };
  783.  
  784. &hdmi_video {
  785. pinctrl-names = "default";
  786. pinctrl-0 = <&pinctrl_hdmi_hdcp_1>;
  787. fsl,hdcp;
  788. status = "okay";
  789. };
  790.  
  791. &hdmi_audio {
  792. status = "okay";
  793. };
  794.  
  795. &spdif {
  796. pinctrl-names = "default";
  797. pinctrl-0 = <&pinctrl_spdif>;
  798. status = "okay";
  799. };
  800.  
  801. &audmux {
  802. pinctrl-names = "default";
  803. pinctrl-0 = <&pinctrl_audmux>;
  804. status = "okay";
  805. };
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