architecture snake of VHDL3Homework is
    signal snake            : std_logic_vector(15 downto 0);

    function isInitialized (snake : std_logic_vector(15 downto 0))
        return boolean is

        variable initialized : boolean;
        begin
            if  (snake(0) = '1') or
                (snake(2) = '1') or
                (snake(4) = '1') or
                (snake(6) = '1') or
                (snake(8) = '1') or
                (snake(10) = '1') or
                (snake(12) = '1') or
                (snake(14) = '1')
            then
                initialized := true;
            else
                initialized := false;
            end if;
        return initialized;
    end function isInitialized;

    begin

        moveSnake : process(CLOCK_27) is
            variable rightDirection : boolean := false;

            begin
                if rising_edge(snakeClock) then


                    if not isInitialized(snake) then    --sem jsem se v debuggeru dostal
                        snake(0) <= '0';        --sem jsem se v debuggeru taky dostal
                        snake(1) <= '0';        --sem taky, prošlo to každý řádek
                        snake(2) <= '0';        --ale proměnná snake se vůbec nezměnila
                        snake(3) <= '0';
                        snake(4) <= '0';
                        snake(5) <= '0';
                        snake(6) <= '0';
                        snake(7) <= '0';
                        snake(8) <= '0';
                        snake(9) <= '0';
                        snake(10) <= '0';
                        snake(11) <= '0';
                        snake(12) <= '0';
                        snake(13) <= '0';
                        snake(14) <= '1';
                        snake(15) <= '1';

                        LEDG(0) <= '1';
                        LEDG(1) <= '0';
                    else
                        LEDG(0) <= '0';
                        LEDG(1) <= '1';
                    end if;