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varli_ketanpl

AC_LAB1_EX4

Oct 11th, 2023
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  1. module comp(
  2.     output lt, eq, gt,
  3.     input a, b);
  4.    
  5.     xnor x1(eq, a, b);
  6.    
  7.     wire o1, o2;
  8.    
  9.     not n1(o1, a);
  10.     not n2(o2, b);
  11.    
  12.     and nd1(lt, o1, b);
  13.     and nd2(gt, o2, a);
  14. endmodule
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