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mpi regs bcm6348

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  1. /* MPI_BASE =  0xfffe2000 */
  2. typedef struct MpiRegisters {
  3.   EbiChipSelect cs[7];                  /*0x0 size chip select configuration (14 uin32)*/
  4. #define EBI_CS0_BASE            0
  5. #define EBI_CS1_BASE            1
  6. #define EBI_CS2_BASE            2
  7. #define EBI_CS3_BASE            3
  8. #define PCMCIA_COMMON_BASE      4
  9. #define PCMCIA_ATTRIBUTE_BASE   5
  10. #define PCMCIA_IO_BASE          6
  11.   uint32        unused0[2];             /*0x38 reserved */
  12.   uint32        ebi_control;            /*0x40 ebi control */
  13.   uint32        unused1[4];             /*0x44 reserved */
  14. #define EBI_ACCESS_TIMEOUT      0x000007FF
  15.   uint32        pcmcia_cntl1;           /*0x54 pcmcia control 1 */
  16. #define PCCARD_CARD_RESET       0x00040000
  17. #define CARDBUS_ENABLE          0x00008000
  18. #define PCMCIA_ENABLE           0x00004000
  19. #define PCMCIA_GPIO_ENABLE      0x00002000
  20. #define CARDBUS_IDSEL           0x00001F00
  21. #define VS2_OEN                 0x00000080
  22. #define VS1_OEN                 0x00000040
  23. #define VS2_OUT                 0x00000020
  24. #define VS1_OUT                 0x00000010
  25. #define VS2_IN                  0x00000008
  26. #define VS1_IN                  0x00000004
  27. #define CD2_IN                  0x00000002
  28. #define CD1_IN                  0x00000001
  29. #define VS_MASK                 0x0000000C
  30. #define CD_MASK                 0x00000003
  31.   uint32        unused2;                /*0x58 reserved */
  32.   uint32        pcmcia_cntl2;           /*0x5c pcmcia control 2 */
  33. #define PCMCIA_BYTESWAP_DIS     0x00000002
  34. #define PCMCIA_HALFWORD_EN      0x00000001
  35. #define RW_ACTIVE_CNT_BIT       2
  36. #define INACTIVE_CNT_BIT        8
  37. #define CE_SETUP_CNT_BIT        16
  38. #define CE_HOLD_CNT_BIT         24
  39.   uint32        unused3[40];            /*0x60 reserved */
  40.  
  41.   uint32        sp0range;               /*0x100 PCI to internal system bus address space */
  42.   uint32        sp0remap;               /*0x104*/
  43.   uint32        sp0cfg;                 /*0x108*/
  44.   uint32        sp1range;               /*0x10c*/
  45.   uint32        sp1remap;               /*0x110*/
  46.   uint32        sp1cfg;                 /*0x114*/
  47.  
  48.   uint32        EndianCfg;              /*0x118*/
  49.  
  50.   uint32        l2pcfgctl;              /*0x11c internal system bus to PCI IO/Cfg control */
  51. #define DIR_CFG_SEL             0x80000000 /* change from PCI I/O access to PCI config access */
  52. #define DIR_CFG_USEREG          0x40000000 /* use this register info for PCI configuration access */
  53. #define DEVICE_NUMBER           0x00007C00 /* device number for the PCI configuration access */
  54. #define FUNC_NUMBER             0x00000300 /* function number for the PCI configuration access */
  55. #define REG_NUMBER              0x000000FC /* register number for the PCI configuration access */
  56. #define CONFIG_TYPE             0x00000003 /* configuration type for the PCI configuration access */
  57.  
  58.   uint32        l2pmrange1;             /*0x120 internal system bus to PCI memory space */
  59. #define PCI_SIZE_64K            0xFFFF0000
  60. #define PCI_SIZE_128K           0xFFFE0000
  61. #define PCI_SIZE_256K           0xFFFC0000
  62. #define PCI_SIZE_512K           0xFFF80000
  63. #define PCI_SIZE_1M             0xFFF00000
  64. #define PCI_SIZE_2M             0xFFE00000
  65. #define PCI_SIZE_4M             0xFFC00000
  66. #define PCI_SIZE_8M             0xFF800000
  67. #define PCI_SIZE_16M            0xFF000000
  68. #define PCI_SIZE_32M            0xFE000000
  69.   uint32        l2pmbase1;              /*0x124 kseg0 or kseg1 address & 0x1FFFFFFF */
  70.   uint32        l2pmremap1;             /*0x128*/
  71. #define CARDBUS_MEM             0x00000004
  72. #define MEM_WINDOW_EN           0x00000001
  73.   uint32        l2pmrange2;             /*0x12c**/
  74.   uint32        l2pmbase2;             /*0x130**/
  75.   uint32        l2pmremap2;             /*0x134**/
  76.   uint32        l2piorange;             /*0x138 internal system bus to PCI I/O space */
  77.   uint32        l2piobase;             /*0x13c**/
  78.   uint32        l2pioremap;             /*0x140**/
  79.  
  80.   uint32        pcimodesel;             /*0x144**/
  81. #define PCI_INT_BUS_RD_PREFETCH 0x000001F0
  82. #define PCI_BAR2_NOSWAP         0x00000002 /* BAR at offset 0x20 */
  83. #define PCI_BAR1_NOSWAP         0x00000001 /* BAR at affset 0x1c */
  84.  
  85.   uint32        pciintstat;             /*0x148 PCI interrupt mask/status */
  86. #define MAILBOX1_SENT           0x08
  87. #define MAILBOX0_SENT           0x04
  88. #define MAILBOX1_MSG_RCV        0x02
  89. #define MAILBOX0_MSG_RCV        0x01
  90.   uint32        locbuscntrl;            /*0x14c internal system bus control */
  91. #define DIR_U2P_NOSWAP          0x00000002
  92. #define EN_PCI_GPIO             0x00000001
  93.   uint32        locintstat;             /*0x150 internal system bus interrupt mask/status */
  94. #define CSERR                   0x0200
  95. #define SERR                    0x0100
  96. #define EXT_PCI_INT             0x0080
  97. #define DIR_FAILED              0x0040
  98. #define DIR_COMPLETE            0x0020
  99. #define PCI_CFG                 0x0010
  100.   uint32        unused5[7];             /*0x154**/
  101.  
  102.   uint32        mailbox0;             /*0x170**/
  103.   uint32        mailbox1;             /*0x174**/
  104.  
  105.   uint32        pcicfgcntrl;            /*0x178 internal system bus PCI configuration control */
  106. #define PCI_CFG_REG_WRITE_EN    0x00000080
  107. #define PCI_CFG_ADDR            0x0000003C
  108.   uint32        pcicfgdata;             /*0x17c internal system bus PCI configuration data */
  109.  
  110.   uint32        locch2ctl;              /*0x180 PCI to interrnal system bus DMA (downstream) local control */
  111. #define MPI_DMA_HALT            0x00000008  /* idle after finish current memory burst */
  112. #define MPI_DMA_PKT_HALT        0x00000004  /* idle after an EOP flag is detected */
  113. #define MPI_DMA_STALL           0x00000002  /* idle after an EOP flag is detected */
  114. #define MPI_DMA_ENABLE          0x00000001  /* set to enable channel */
  115.   uint32        locch2intStat;           /*0x184*/
  116. #define MPI_DMA_NO_DESC         0x00000004  /* no valid descriptors */
  117. #define MPI_DMA_DONE            0x00000002  /* packet xfer complete */
  118. #define MPI_DMA_BUFF_DONE       0x00000001  /* buffer done */
  119.   uint32        locch2intMask;
  120.   uint32        unused6;
  121.   uint32        locch2descaddr;
  122.   uint32        locch2status1;
  123. #define LOCAL_DESC_STATE        0xE0000000
  124. #define PCI_DESC_STATE          0x1C000000
  125. #define BYTE_DONE               0x03FFC000
  126. #define RING_ADDR               0x00003FFF
  127.   uint32        locch2status2;
  128. #define BUFPTR_OFFSET           0x1FFF0000
  129. #define PCI_MASTER_STATE        0x000000C0
  130. #define LOC_MASTER_STATE        0x00000038
  131. #define CONTROL_STATE           0x00000007
  132.   uint32        unused7;
  133.  
  134.   uint32        locch1Ctl;              /*internal system bus to PCI DMA (upstream) local control */
  135. #define DMA_U2P_LE              0x00000200  /* local bus is little endian */
  136. #define DMA_U2P_NOSWAP          0x00000100  /* lccal bus is little endian but no data swapped */
  137.   uint32        locch1intstat;
  138.   uint32        locch1intmask;
  139.   uint32        unused8;
  140.   uint32        locch1descaddr;
  141.   uint32        locch1status1;
  142.   uint32        locch1status2;
  143.   uint32        unused9;
  144.  
  145.   uint32        pcich1ctl;              /* internal system bus to PCI DMA PCI control */
  146.   uint32        pcich1intstat;
  147.   uint32        pcich1intmask;
  148.   uint32        pcich1descaddr;
  149.   uint32        pcich1status1;
  150.   uint32        pcich1status2;
  151.  
  152.   uint32        pcich2Ctl;              /* PCI to internal system bus DMA PCI control */
  153.   uint32        pcich2intstat;
  154.   uint32        pcich2intmask;
  155.   uint32        pcich2descaddr;
  156.   uint32        pcich2status1;
  157.   uint32        pcich2status2;
  158.  
  159.   uint32        perm_id;                /* permanent device and vendor id */
  160.   uint32        perm_rev;               /* permanent revision id */
  161. } MpiRegisters;
  162.  
  163. #define MPI ((volatile MpiRegisters * const) MPI_BASE)
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