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- From c0d6cfee13baba2aadc7704b70faafb879ec615b Mon Sep 17 00:00:00 2001
- From: "Alex L. White" <space.monkey.delivers@gmail.com>
- Date: Tue, 17 May 2016 13:13:15 +0300
- Subject: [PATCH] Introducing 4 state branch predictor
- ---
- rtl/verilog/mor1kx_branch_prediction.v | 71 +++++++++++++++-----
- .../mor1kx_branch_predictor_saturation_counter.v | 77 ++++++++++++++++++++++
- rtl/verilog/mor1kx_branch_predictor_simple.v | 36 ++++++++++
- rtl/verilog/mor1kx_cpu_cappuccino.v | 7 +-
- 4 files changed, 172 insertions(+), 19 deletions(-)
- create mode 100644 rtl/verilog/mor1kx_branch_predictor_saturation_counter.v
- create mode 100644 rtl/verilog/mor1kx_branch_predictor_simple.v
- diff --git a/rtl/verilog/mor1kx_branch_prediction.v b/rtl/verilog/mor1kx_branch_prediction.v
- index a82c1f9..0cf674a 100644
- --- a/rtl/verilog/mor1kx_branch_prediction.v
- +++ b/rtl/verilog/mor1kx_branch_prediction.v
- @@ -18,35 +18,72 @@
- module mor1kx_branch_prediction
- #(
- - parameter OPTION_OPERAND_WIDTH = 32
- + parameter OPTION_OPERAND_WIDTH = 32,
- + parameter FEATURE_PREDICTOR_TYPE = "NONE"
- )
- (
- - input clk,
- - input rst,
- + input clk,
- + input rst,
- // Signals belonging to the stage where the branch is predicted.
- - input op_bf_i,
- - input op_bnf_i,
- - input [9:0] immjbr_upper_i,
- - output predicted_flag_o,
- + input op_bf_i, // branch if flag
- + input op_bnf_i, // branch if not flag
- + input [9:0] immjbr_upper_i, // branch offset
- + output predicted_flag_o, //result of predictor
- // Signals belonging to the stage where the branch is resolved.
- - input prev_op_brcond_i,
- - input prev_predicted_flag_i,
- - input flag_i,
- + input prev_op_brcond_i, // prev op was cond brn
- + input prev_predicted_flag_i, // prev insn predicated flag
- + input flag_i, // prev insn real flag
- // Branch misprediction indicator
- - output branch_mispredict_o
- + output branch_mispredict_o // result of prediction
- );
- // Compare the real flag with the previously predicted flag and signal a
- // misprediction in case of a mismatch.
- assign branch_mispredict_o = prev_op_brcond_i &
- - (flag_i != prev_predicted_flag_i);
- -
- - // Static branch prediction - backward branches are predicted as taken,
- - // forward branches as not taken.
- - assign predicted_flag_o = op_bf_i & immjbr_upper_i[9] |
- - op_bnf_i & !immjbr_upper_i[9];
- + (flag_i != prev_predicted_flag_i);
- +
- +generate
- +if (FEATURE_PREDICTOR_TYPE=="SATURATION_COUNTER") begin : branch_predictor_saturation_counter
- + mor1kx_branch_predictor_saturation_counter
- + #(
- + .OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH)
- + )
- + mor1kx_branch_predictor_saturation_counter
- + (
- + // Outputs
- + .predicted_flag_o (predicted_flag_o),
- + // Inputs
- + .clk (clk),
- + .rst (rst),
- + .prev_op_brcond_i (prev_op_brcond_i),
- + .branch_mispredict_i (branch_mispredict_o));
- +
- +end else if (FEATURE_PREDICTOR_TYPE=="SIMPLE") begin : branch_predictor_simple
- + mor1kx_branch_predictor_simple
- + #(
- + .OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH)
- + )
- + mor1kx_branch_predictor_simple
- + (
- + // Outputs
- + .predicted_flag_o (predicted_flag_o),
- + // Inputs
- + .clk (clk),
- + .rst (rst),
- + .op_bf_i (op_bf_i),
- + .op_bnf_i (op_bnf_i),
- + .immjbr_upper_i (immjbr_upper_i));
- +
- +end else if (FEATURE_PREDICTOR_TYPE!="SIMPLE" &&
- + FEATURE_PREDICTOR_TYPE!="SATURATION_COUNTER") begin
- + initial begin
- + $display("Error: FEATURE_PREDICTOR_TYPE, %s, not valid", FEATURE_PREDICTOR_TYPE);
- + $finish();
- + end
- +end
- +endgenerate
- endmodule
- diff --git a/rtl/verilog/mor1kx_branch_predictor_saturation_counter.v b/rtl/verilog/mor1kx_branch_predictor_saturation_counter.v
- new file mode 100644
- index 0000000..34b235d
- --- /dev/null
- +++ b/rtl/verilog/mor1kx_branch_predictor_saturation_counter.v
- @@ -0,0 +1,77 @@
- +/******************************************************************************
- + This Source Code Form is subject to the terms of the
- + Open Hardware Description License, v. 1.0. If a copy
- + of the OHDL was not distributed with this file, You
- + can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
- +
- + Description: Branch prediction module
- + Generates a predicted flag output and compares that to the real flag
- + when it comes back in the following pipeline stage.
- + Signals are deliberately not named after the pipeline stage they belong to,
- + in order to keep this module generic.
- +
- + Copyright (C) 2013 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
- +
- + ******************************************************************************/
- +
- +`include "mor1kx-defines.v"
- +
- +module mor1kx_branch_predictor_saturation_counter
- + #(
- + parameter OPTION_OPERAND_WIDTH = 32
- + )
- + (
- + input clk,
- + input rst,
- +
- + // Signals belonging to the stage where the branch is predicted.
- + output predicted_flag_o, //result of predictor
- +
- + // Signals belonging to the stage where the branch is resolved.
- + input prev_op_brcond_i, // prev op was cond brn
- + input branch_mispredict_i // prev brn was mispredicted
- + );
- +
- + localparam [1:0]
- + STATE_STRONGLY_NOT_TAKEN = 2'b00,
- + STATE_WEAKLY_NOT_TAKEN = 2'b01,
- + STATE_WEAKLY_TAKEN = 2'b10,
- + STATE_STRONGLY_TAKEN = 2'b11;
- +
- + reg [1:0] state = STATE_WEAKLY_TAKEN;
- +
- + assign predicted_flag_o = state[1];
- +
- + always @(posedge clk) begin
- + if (rst) begin
- + // set default state to STATE_WEAKLY_TAKEN
- + state <= STATE_WEAKLY_TAKEN;
- + end else begin
- + // if prev insn was a branch
- + if (prev_op_brcond_i) begin
- + // if it was mispredicted
- + if (branch_mispredict_i) begin
- + // change fsm state:
- + // STATE_STRONGLY_TAKEN -> STATE_WEAKLY_TAKEN
- + // STATE_WEAKLY_TAKEN -> STATE_WEAKLY_NOT_TAKEN
- + // STATE_WEAKLY_NOT_TAKEN -> STATE_STRONGLY_NOT_TAKEN
- + // STATE_STRONGLY_NOT_TAKEN -> STATE_STRONGLY_NOT_TAKEN
- + state <= (state == STATE_STRONGLY_TAKEN) ? STATE_WEAKLY_TAKEN :
- + (state == STATE_WEAKLY_TAKEN) ? STATE_WEAKLY_NOT_TAKEN
- + : STATE_STRONGLY_NOT_TAKEN;
- + // if prev insn was predicted correctly
- + end else begin
- + // change fsm state:
- + // STATE_STRONGLY_NOT_TAKEN -> STATE_WEAKLY_NOT_TAKEN
- + // STATE_WEAKLY_NOT_TAKEN -> STATE_WEAKLY_TAKEN
- + // STATE_WEAKLY_TAKEN -> STATE_STRONGLY_TAKEN
- + // STATE_STRONGLY_TAKEN -> STATE_STRONGLY_TAKEN
- + state <= (state == STATE_STRONGLY_NOT_TAKEN) ? STATE_WEAKLY_NOT_TAKEN :
- + (state == STATE_WEAKLY_NOT_TAKEN) ? STATE_WEAKLY_TAKEN
- + : STATE_STRONGLY_TAKEN;
- + end
- + end
- + end
- + end
- +
- +endmodule
- diff --git a/rtl/verilog/mor1kx_branch_predictor_simple.v b/rtl/verilog/mor1kx_branch_predictor_simple.v
- new file mode 100644
- index 0000000..8ad2f08
- --- /dev/null
- +++ b/rtl/verilog/mor1kx_branch_predictor_simple.v
- @@ -0,0 +1,36 @@
- +/******************************************************************************
- + This Source Code Form is subject to the terms of the
- + Open Hardware Description License, v. 1.0. If a copy
- + of the OHDL was not distributed with this file, You
- + can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
- +
- + Description: Branch prediction module
- + Generates a predicted flag output and compares that to the real flag
- + when it comes back in the following pipeline stage.
- + Signals are deliberately not named after the pipeline stage they belong to,
- + in order to keep this module generic.
- +
- + Copyright (C) 2013 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
- +
- + ******************************************************************************/
- +
- +`include "mor1kx-defines.v"
- +
- +module mor1kx_branch_predictor_simple
- + #(
- + parameter OPTION_OPERAND_WIDTH = 32
- + )
- + (
- + // Signals belonging to the stage where the branch is predicted.
- + input op_bf_i, // branch if flag
- + input op_bnf_i, // branch if not flag
- + input [9:0] immjbr_upper_i, // branch offset
- + output predicted_flag_o //result of predictor
- + );
- +
- + // Static branch prediction - backward branches are predicted as taken,
- + // forward branches as not taken.
- + assign predicted_flag_o = op_bf_i & immjbr_upper_i[9] |
- + op_bnf_i & !immjbr_upper_i[9];
- +
- +endmodule
- diff --git a/rtl/verilog/mor1kx_cpu_cappuccino.v b/rtl/verilog/mor1kx_cpu_cappuccino.v
- index f282374..5628f69 100644
- --- a/rtl/verilog/mor1kx_cpu_cappuccino.v
- +++ b/rtl/verilog/mor1kx_cpu_cappuccino.v
- @@ -96,7 +96,9 @@ module mor1kx_cpu_cappuccino
- parameter FEATURE_MULTICORE = "NONE",
- - parameter FEATURE_TRACEPORT_EXEC = "NONE"
- + parameter FEATURE_TRACEPORT_EXEC = "NONE",
- +
- + parameter FEATURE_PREDICTOR_TYPE = "SIMPLE" // SIMPLE|SATURATION_COUNTER
- )
- (
- input clk,
- @@ -752,7 +754,8 @@ module mor1kx_cpu_cappuccino
- );*/
- mor1kx_branch_prediction
- #(
- - .OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH)
- + .OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH),
- + .FEATURE_PREDICTOR_TYPE(FEATURE_PREDICTOR_TYPE)
- )
- mor1kx_branch_prediction
- (/*AUTOINST*/
- --
- 1.9.1
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