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  1. From c0d6cfee13baba2aadc7704b70faafb879ec615b Mon Sep 17 00:00:00 2001
  2. From: "Alex L. White" <space.monkey.delivers@gmail.com>
  3. Date: Tue, 17 May 2016 13:13:15 +0300
  4. Subject: [PATCH] Introducing 4 state branch predictor
  5.  
  6. ---
  7.  rtl/verilog/mor1kx_branch_prediction.v             | 71 +++++++++++++++-----
  8.  .../mor1kx_branch_predictor_saturation_counter.v   | 77 ++++++++++++++++++++++
  9.  rtl/verilog/mor1kx_branch_predictor_simple.v       | 36 ++++++++++
  10.  rtl/verilog/mor1kx_cpu_cappuccino.v                |  7 +-
  11.  4 files changed, 172 insertions(+), 19 deletions(-)
  12.  create mode 100644 rtl/verilog/mor1kx_branch_predictor_saturation_counter.v
  13.  create mode 100644 rtl/verilog/mor1kx_branch_predictor_simple.v
  14.  
  15. diff --git a/rtl/verilog/mor1kx_branch_prediction.v b/rtl/verilog/mor1kx_branch_prediction.v
  16. index a82c1f9..0cf674a 100644
  17. --- a/rtl/verilog/mor1kx_branch_prediction.v
  18. +++ b/rtl/verilog/mor1kx_branch_prediction.v
  19. @@ -18,35 +18,72 @@
  20.  
  21.  module mor1kx_branch_prediction
  22.    #(
  23. -    parameter OPTION_OPERAND_WIDTH = 32
  24. +    parameter OPTION_OPERAND_WIDTH = 32,
  25. +    parameter FEATURE_PREDICTOR_TYPE = "NONE"
  26.      )
  27.     (
  28. -    input  clk,
  29. -    input  rst,
  30. +    input clk,
  31. +    input rst,
  32.  
  33.      // Signals belonging to the stage where the branch is predicted.
  34. -    input  op_bf_i,
  35. -    input  op_bnf_i,
  36. -    input [9:0] immjbr_upper_i,
  37. -    output     predicted_flag_o,
  38. +    input op_bf_i,               // branch if flag
  39. +    input op_bnf_i,              // branch if not flag
  40. +    input [9:0] immjbr_upper_i,  // branch offset
  41. +    output predicted_flag_o,     //result of predictor
  42.  
  43.      // Signals belonging to the stage where the branch is resolved.
  44. -    input  prev_op_brcond_i,
  45. -    input  prev_predicted_flag_i,
  46. -    input  flag_i,
  47. +    input prev_op_brcond_i,      // prev op was cond brn
  48. +    input prev_predicted_flag_i, // prev insn predicated flag
  49. +    input flag_i,                // prev insn real flag
  50.  
  51.      // Branch misprediction indicator
  52. -    output     branch_mispredict_o
  53. +    output branch_mispredict_o   // result of prediction
  54.      );
  55.  
  56.     // Compare the real flag with the previously predicted flag and signal a
  57.     // misprediction in case of a mismatch.
  58.     assign branch_mispredict_o = prev_op_brcond_i &
  59. -               (flag_i != prev_predicted_flag_i);
  60. -
  61. -   // Static branch prediction - backward branches are predicted as taken,
  62. -   // forward branches as not taken.
  63. -   assign predicted_flag_o = op_bf_i & immjbr_upper_i[9] |
  64. -                op_bnf_i & !immjbr_upper_i[9];
  65. +                                (flag_i != prev_predicted_flag_i);
  66. +  
  67. +generate
  68. +if (FEATURE_PREDICTOR_TYPE=="SATURATION_COUNTER") begin : branch_predictor_saturation_counter
  69. +   mor1kx_branch_predictor_saturation_counter
  70. +     #(
  71. +       .OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH)
  72. +       )
  73. +      mor1kx_branch_predictor_saturation_counter
  74. +      (
  75. +       // Outputs
  76. +       .predicted_flag_o                 (predicted_flag_o),
  77. +       // Inputs
  78. +       .clk                              (clk),
  79. +       .rst                              (rst),
  80. +       .prev_op_brcond_i                 (prev_op_brcond_i),
  81. +       .branch_mispredict_i              (branch_mispredict_o));
  82. +      
  83. +end else if (FEATURE_PREDICTOR_TYPE=="SIMPLE") begin : branch_predictor_simple
  84. +   mor1kx_branch_predictor_simple
  85. +     #(
  86. +       .OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH)
  87. +       )
  88. +      mor1kx_branch_predictor_simple
  89. +      (
  90. +       // Outputs
  91. +       .predicted_flag_o                 (predicted_flag_o),
  92. +       // Inputs
  93. +       .clk                              (clk),
  94. +       .rst                              (rst),
  95. +       .op_bf_i                          (op_bf_i),
  96. +       .op_bnf_i                         (op_bnf_i),
  97. +       .immjbr_upper_i                   (immjbr_upper_i));
  98. +        
  99. +end else if (FEATURE_PREDICTOR_TYPE!="SIMPLE" &&
  100. +             FEATURE_PREDICTOR_TYPE!="SATURATION_COUNTER") begin
  101. +   initial begin
  102. +      $display("Error: FEATURE_PREDICTOR_TYPE, %s, not valid", FEATURE_PREDICTOR_TYPE);
  103. +      $finish();
  104. +   end
  105. +end
  106. +endgenerate
  107.  
  108.  endmodule
  109. diff --git a/rtl/verilog/mor1kx_branch_predictor_saturation_counter.v b/rtl/verilog/mor1kx_branch_predictor_saturation_counter.v
  110. new file mode 100644
  111. index 0000000..34b235d
  112. --- /dev/null
  113. +++ b/rtl/verilog/mor1kx_branch_predictor_saturation_counter.v
  114. @@ -0,0 +1,77 @@
  115. +/******************************************************************************
  116. + This Source Code Form is subject to the terms of the
  117. + Open Hardware Description License, v. 1.0. If a copy
  118. + of the OHDL was not distributed with this file, You
  119. + can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
  120. +
  121. + Description: Branch prediction module
  122. + Generates a predicted flag output and compares that to the real flag
  123. + when it comes back in the following pipeline stage.
  124. + Signals are deliberately not named after the pipeline stage they belong to,
  125. + in order to keep this module generic.
  126. +
  127. + Copyright (C) 2013 Stefan Kristiansson <[email protected]>
  128. +
  129. + ******************************************************************************/
  130. +
  131. +`include "mor1kx-defines.v"
  132. +
  133. +module mor1kx_branch_predictor_saturation_counter
  134. +  #(
  135. +    parameter OPTION_OPERAND_WIDTH = 32
  136. +    )
  137. +   (
  138. +    input clk,
  139. +    input rst,
  140. +
  141. +    // Signals belonging to the stage where the branch is predicted.
  142. +    output predicted_flag_o,     //result of predictor
  143. +
  144. +    // Signals belonging to the stage where the branch is resolved.
  145. +    input prev_op_brcond_i,      // prev op was cond brn
  146. +    input branch_mispredict_i    // prev brn was mispredicted
  147. +    );
  148. +
  149. +   localparam [1:0]
  150. +      STATE_STRONGLY_NOT_TAKEN = 2'b00,
  151. +      STATE_WEAKLY_NOT_TAKEN   = 2'b01,
  152. +      STATE_WEAKLY_TAKEN       = 2'b10,
  153. +      STATE_STRONGLY_TAKEN     = 2'b11;
  154. +
  155. +   reg [1:0] state = STATE_WEAKLY_TAKEN;
  156. +
  157. +   assign predicted_flag_o = state[1];
  158. +
  159. +   always @(posedge clk) begin
  160. +      if (rst) begin
  161. +         // set default state to STATE_WEAKLY_TAKEN
  162. +         state <= STATE_WEAKLY_TAKEN;
  163. +      end else begin
  164. +         // if prev insn was a branch
  165. +         if (prev_op_brcond_i) begin
  166. +            // if it was mispredicted
  167. +            if (branch_mispredict_i) begin
  168. +               // change fsm state:
  169. +               //   STATE_STRONGLY_TAKEN -> STATE_WEAKLY_TAKEN
  170. +               //   STATE_WEAKLY_TAKEN -> STATE_WEAKLY_NOT_TAKEN
  171. +               //   STATE_WEAKLY_NOT_TAKEN -> STATE_STRONGLY_NOT_TAKEN
  172. +               //   STATE_STRONGLY_NOT_TAKEN -> STATE_STRONGLY_NOT_TAKEN
  173. +               state <= (state == STATE_STRONGLY_TAKEN) ? STATE_WEAKLY_TAKEN :
  174. +                        (state == STATE_WEAKLY_TAKEN)   ? STATE_WEAKLY_NOT_TAKEN
  175. +                                                        : STATE_STRONGLY_NOT_TAKEN;
  176. +            // if prev insn was predicted correctly                                        
  177. +            end else begin
  178. +               // change fsm state:
  179. +               //   STATE_STRONGLY_NOT_TAKEN -> STATE_WEAKLY_NOT_TAKEN
  180. +               //   STATE_WEAKLY_NOT_TAKEN -> STATE_WEAKLY_TAKEN
  181. +               //   STATE_WEAKLY_TAKEN -> STATE_STRONGLY_TAKEN
  182. +               //   STATE_STRONGLY_TAKEN -> STATE_STRONGLY_TAKEN
  183. +               state <= (state == STATE_STRONGLY_NOT_TAKEN) ? STATE_WEAKLY_NOT_TAKEN :
  184. +                        (state == STATE_WEAKLY_NOT_TAKEN)   ? STATE_WEAKLY_TAKEN
  185. +                                                            : STATE_STRONGLY_TAKEN;
  186. +            end
  187. +         end
  188. +      end
  189. +   end
  190. +
  191. +endmodule
  192. diff --git a/rtl/verilog/mor1kx_branch_predictor_simple.v b/rtl/verilog/mor1kx_branch_predictor_simple.v
  193. new file mode 100644
  194. index 0000000..8ad2f08
  195. --- /dev/null
  196. +++ b/rtl/verilog/mor1kx_branch_predictor_simple.v
  197. @@ -0,0 +1,36 @@
  198. +/******************************************************************************
  199. + This Source Code Form is subject to the terms of the
  200. + Open Hardware Description License, v. 1.0. If a copy
  201. + of the OHDL was not distributed with this file, You
  202. + can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
  203. +
  204. + Description: Branch prediction module
  205. + Generates a predicted flag output and compares that to the real flag
  206. + when it comes back in the following pipeline stage.
  207. + Signals are deliberately not named after the pipeline stage they belong to,
  208. + in order to keep this module generic.
  209. +
  210. + Copyright (C) 2013 Stefan Kristiansson <[email protected]>
  211. +
  212. + ******************************************************************************/
  213. +
  214. +`include "mor1kx-defines.v"
  215. +
  216. +module mor1kx_branch_predictor_simple
  217. +  #(
  218. +    parameter OPTION_OPERAND_WIDTH = 32
  219. +    )
  220. +   (
  221. +    // Signals belonging to the stage where the branch is predicted.
  222. +    input op_bf_i,               // branch if flag
  223. +    input op_bnf_i,              // branch if not flag
  224. +    input [9:0] immjbr_upper_i,  // branch offset
  225. +    output predicted_flag_o      //result of predictor
  226. +    );
  227. +  
  228. +   // Static branch prediction - backward branches are predicted as taken,
  229. +   // forward branches as not taken.
  230. +   assign predicted_flag_o = op_bf_i & immjbr_upper_i[9] |
  231. +                             op_bnf_i & !immjbr_upper_i[9];
  232. +
  233. +endmodule
  234. diff --git a/rtl/verilog/mor1kx_cpu_cappuccino.v b/rtl/verilog/mor1kx_cpu_cappuccino.v
  235. index f282374..5628f69 100644
  236. --- a/rtl/verilog/mor1kx_cpu_cappuccino.v
  237. +++ b/rtl/verilog/mor1kx_cpu_cappuccino.v
  238. @@ -96,7 +96,9 @@ module mor1kx_cpu_cappuccino
  239.  
  240.      parameter FEATURE_MULTICORE = "NONE",
  241.  
  242. -    parameter FEATURE_TRACEPORT_EXEC = "NONE"
  243. +    parameter FEATURE_TRACEPORT_EXEC = "NONE",
  244. +    
  245. +    parameter FEATURE_PREDICTOR_TYPE = "SIMPLE" // SIMPLE|SATURATION_COUNTER
  246.      )
  247.     (
  248.      input                clk,
  249. @@ -752,7 +754,8 @@ module mor1kx_cpu_cappuccino
  250.      );*/
  251.     mor1kx_branch_prediction
  252.       #(
  253. -       .OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH)
  254. +       .OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH),
  255. +       .FEATURE_PREDICTOR_TYPE(FEATURE_PREDICTOR_TYPE)
  256.         )
  257.     mor1kx_branch_prediction
  258.       (/*AUTOINST*/
  259. --
  260. 1.9.1
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