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// VHDL Custom Instruction Template File for Combinatorial Logic

module ycbcr_to_rgb (
dataa,  // Operand A (always required)
        // dataa(7 downto 0) contains Y
datab,  // Operand B (optional)
        //datab(7 downto 0) contains Cb
        // datab(15 downto 8) contains Cr
result, // result (always required)
);

input dataa[31:0];
input datab[31:0];

output result[31:0];

// Intermediate signals
reg signed [7:0] Cbb;
reg signed [7:0] Crr;
reg [23:0] YYstd;
reg signed [23:0] YY;

reg signed [23:0] Cr1402;
reg signed [22:0] Cr071414;
reg signed [21:0] Cb034414;
reg signed [23:0] Cb1722;

reg signed [23:0] red24;
reg signed [23:0] blue24;
reg signed [23:0] green24;

parameter c22970 = 16'b0101100110111010;
parameter c11700 = 15'b010110110110100;
parameter c5638  = 14'b01011000000110;
parameter c29032 = 16'b0111000101101000;

always @(*) begin
    YYstd = {2'b0, dataa, 14'b0};
    YY = YYstd;
    Cbb = {~datab[7], datab[6:0]}; // --subtract 128
    Crr = {~datab[15], datab[14:0]};

    Cr1402 = Crr * c22970;
    Cr071414 = Crr * c11700;
    Cb034414 = Cbb * c5638;
    Cb1722 = Cbb * c29032;

    red24 = YY + Cr1402;
    blue24 = YY + Cb1722;
    green24 = YY - Cb034414 - Cr071414;

    result[31:24] = '0;

    if (blue24[23]) begin
        result[7:0] = '0;
    end else if (blue24[22]) begin
        result[7:0] = '1;
    end else begin
        result[7:0] = blue24[21:14];
    end;

    if (green24[23]) begin
        result[15:8] = '0;
    end else if (green24[22]) begin
        result[15:8] = '1;
    end else begin
        result[15:8] = green24[21:14];
    end;

    if (red24[23]) begin
        result[23:16] = '0;
    end else if (red24[22]) begin
        result[23:16] = '1;
    end else begin
        result[23:16] = red24[21:14];
    end;
end

// custom instruction logic (note:  external interfaces can be used as well)
// use the n[7..0] port as a select signal on a multiplexer to select the value to feed result[31..0]
endmodule;