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-- Company:
-- Engineer:
--
-- Create Date:    08:48:18 02/23/2017
-- Design Name:
-- Module Name:    SumatorBinar8biti - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity SumatorBinar8biti is
    Port ( iaY : in  STD_LOGIC_VECTOR (7 downto 0);
           iaX : in  STD_LOGIC_VECTOR (7 downto 0);
           oaS : out  STD_LOGIC_VECTOR (7 downto 0);
              iCin : in STD_LOGIC;
              oCout : out STD_LOGIC
              );
end SumatorBinar8biti;

architecture Behavioral of SumatorBinar8biti is

signal saTemp : STD_LOGIC_VECTOR (8 downto 0);

begin


saTemp <= ('0' & iaX) + ('0' & iaY) + iCin;
oaS <= saTemp (7 downto 0);
oCout <= saTemp(8);


end Behavioral;