library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity N_AND is
    generic(N: integer);
     port(
     in1 : in STD_LOGIC_vector(0 to N-1);
     out1 : inout STD_LOGIC
         );
end N_AND;

architecture N_AND of N_AND is
begin
    process(in1)
    variable val: std_logic;
    begin
        val:= in1(0);
        for i in 1 to N-1 loop
            val:= val and in1(i);
        end loop;
        val:= not val;
        if  (out1='0' and val='1') then out1<= val after 2 ns;
            elsif (out1='1' and val='0') then out1<=val after 4 ns;
                else out1<=val;
        end if;
    end process;
end N_AND;

library ieee;
use ieee. std_logic_1164.all;
entity JK_FF is
    port( J,K,C: in std_logic;
          Q, nQ: inout std_logic);
end JK_FF;

architecture structural of JK_FF is
    component N_AND
        generic(N: integer);
        port(IN1 :in std_logic_vector(0 to N-1);
             OUT1: inout std_logic);
    end component;

function DoVector2(IN1,IN2: in std_logic)
    return std_logic_vector is
    variable vec: std_logic_vector(0 to 1);
    begin
    vec(0):=IN1;
    vec(1):=IN2;
    return vec;
    end function;

function DoVector3(IN1,IN2,IN3: in std_logic)
    return std_logic_vector is
    variable vec: std_logic_vector(0 to 2);
    begin
    vec(0):=IN1;
    vec(1):=IN2;
    vec(2):=IN3;
    return vec;
end function;

signal DD1_out, DD2_out, DD3_out, DD4_out, DD5_out, DD6_out: std_logic;
signal DD1_in, DD2_in : std_logic_vector (0 to 2);
signal DD3_in, DD4_in,DD5_in,DD6_in,DD7_in,DD8_in : std_logic_vector (0 to 1);
signal notC,q1,q2: std_logic;

begin
    notC <= not(C);

    DD1_in <= DoVector3(nQ,J,C);
    DD1: N_AND generic map (N=>3)
    port map (in1=>DD1_in,out1=>DD1_out);

    DD2_in <= DoVector3(C,K,Q);
    DD2: N_AND generic map (N=>3)
    port map (in1=>DD2_in,out1=>DD2_out);

    DD3_in <= DoVector2(DD1_out,DD4_out);
    DD3: N_AND generic map (N=>2)
    port map (in1=>DD3_in,out1=>DD3_out);

    DD4_in <= DoVector2(DD3_out,DD2_out);
    DD4: N_AND generic map (N=>2)
    port map (in1=>DD4_in,out1=>DD4_out);

    DD5_in <= DoVector2(DD3_out,notC);
    DD5: N_AND generic map (N=>2)
    port map (in1=>DD5_in,out1=>DD5_out);

    DD6_in <= DoVector2(notC,DD4_out);
    DD6: N_AND generic map (N=>2)
    port map (in1=>DD6_in,out1=>DD6_out);

    DD7_in <= DoVector2(DD5_out,nQ);
    DD7: N_AND generic map (N=>2)
    port map (in1=>DD7_in,out1=>Q);

    DD8_in <= DoVector2(Q,DD6_out);
    DD8: N_AND generic map (N=>2)
    port map (in1=>DD8_in,out1=>nQ);

end structural;