/* Lighweight arbiter between instruction and data busses going
    into the cellram controller */
reg [9:0] cellram_arb_timeout;

always @(posedge wb_clk)
 if (wb_rst)
   cellram_arb_timeout <= 0;
 else if (wb_s2m_mem_ack)
   cellram_arb_timeout <= 0;
 else if (wb_m2s_mem_stb & wb_m2s_mem_cyc)
   cellram_arb_timeout <= cellram_arb_timeout + 1;

assign cellram_arb_reset = (&cellram_arb_timeout);

cellram_ctrl
 /* Use the simple flash interface */
 #(
   .cellram_read_cycles(11), // 70ns in cycles, at 100MHz = 7 (70 ns)
   .cellram_write_cycles(11)) // 70ns in cycles, at 100Mhz = 7 (70 ns)
 cellram_ctrl0
 (
  .wb_clk_i(wb_clk),
  .wb_rst_i(wb_rst | cellram_arb_reset),

  .wb_adr_i(wb_m2s_mem_adr),
  .wb_dat_i(wb_m2s_mem_dat),
  .wb_stb_i(wb_m2s_mem_stb),
  .wb_cyc_i(wb_m2s_mem_cyc),
  .wb_we_i (wb_m2s_mem_we ),
  .wb_sel_i(wb_m2s_mem_sel),
  .wb_dat_o(wb_s2m_mem_dat),
  .wb_ack_o(wb_s2m_mem_ack),
  .wb_err_o(wb_s2m_mem_err),
  .wb_rty_o(wb_s2m_mem_rty),

  .cellram_dq_io(cellram_data_io),
  .cellram_adr_o(cellram_adr_o),
  .cellram_adv_n_o(cellram_adv_n_o),
  .cellram_ce_n_o(cellram_ce_n_o),
  .cellram_clk_o(cellram_clk_o),
  .cellram_oe_n_o(cellram_oe_n_o),
  .cellram_rst_n_o(),
  .cellram_wait_i(cellram_wait_i),
  .cellram_we_n_o(cellram_we_n_o),
  .cellram_wp_n_o(),
  .cellram_lb_n_o(cellram_lb_n_o),
  .cellram_ub_n_o(cellram_ub_n_o),
  .cellram_cre_o(cellram_cre_o)
  );