library IEEE;
use ieee.std_logic_1164.all;

entity desloca is
	generic (
			n: integer := 16
		);
		port (
			a : in std_logic_vector(n-1 downto 0);
			ent : in std_logic;
			q : out std_logic_vector (n-1 downto 0)
		);
end desloca;

architecture comport of desloca is
	begin
		q(3) <= a(2);
		q(2) <= a(1);
		q(1) <= a(0);
		q(0) <= ent;
end comport;

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library IEEE;
use ieee.std_logic_1164.all;

entity deslocador is
	generic (
		gen : integer := 4
	);

	port (
		A : in std_logic_vector (gen-1 downto 0);
		ENT : in std_logic;
		Q : out std_logic_vector (gen-1 downto 0)
	);
end deslocador;

architecture rtl of deslocador is
	component desloca is
		generic (
			n: integer := 16
		);
		port (
			a : in std_logic_vector(n-1 downto 0);
			ent : in std_logic;
			q : out std_logic_vector (n-1 downto 0)
		);
	end component;

begin
r1 : desloca
	generic map(
		n => gen
	)

	port map (
		a => A,
		ent => ENT,
		q => Q
	);
end rtl;