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  1. tridentsx@Fatix:~/dev/my-boot$ cat board/hantek/hdg2002b/hdg2002b_spl.c
  2. /*
  3.  * (C) Copyright 2012 INOV - INESC Inovacao
  4.  * Jose Goncalves <jose.goncalves@inov.pt>
  5.  *
  6.  * See file CREDITS for list of people who contributed to this
  7.  * project.
  8.  *
  9.  * This program is free software; you can redistribute it and/or
  10.  * modify it under the terms of the GNU General Public License as
  11.  * published by the Free Software Foundation; either version 2 of
  12.  * the License, or (at your option) any later version.
  13.  *
  14.  * This program is distributed in the hope that it will be useful,
  15.  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17.  * GNU General Public License for more details.
  18.  *
  19.  * You should have received a copy of the GNU General Public License
  20.  * along with this program; if not, write to the Free Software
  21.  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22.  * MA 02111-1307 USA
  23.  */
  24.  
  25.  /* Next step check the status codes, verify that same external crystal is used in mini2416 as in tq2416
  26.   * Verify the dram timings from the tq2416 code or the openocd configs
  27.   * hook up scope to tx pin and see if anything is printed at all
  28.   */
  29.  
  30. #include <common.h>
  31. #include <spl.h>
  32. #include <version.h>
  33. #include <nand.h>
  34. #include <asm/io.h>
  35. #include <asm/arch/s3c24xx_cpu.h>
  36.  
  37. /* FCLK = 800 MHz, HCLK = 133 MHz, PCLK = 66 MHz */
  38. #define M_MDIV  400
  39. #define M_PDIV  3
  40. #define M_SDIV  1
  41. #define ARMDIV  1
  42. #define PREDIV  2
  43. #define HCLKDIV 1
  44. #define M_LTIME 0x0E10
  45.  
  46. /* EPLLclk = 96MHz */
  47. #define E_MDIV  32
  48. #define E_PDIV  1
  49. #define E_SDIV  2
  50. #define E_LTIME 0x1780
  51.  
  52. DECLARE_GLOBAL_DATA_PTR;
  53.  
  54.  
  55. #define BLINK_INTERVAL 7000000
  56.  
  57. /* TODO
  58.  * Go chasing pointer values now that I have a way to proint them in one go
  59.  */
  60.  
  61.  
  62.  
  63.  
  64. void display_status(int status)
  65. {
  66.         struct s3c24xx_gpio *const gpio = s3c24xx_get_base_gpio();
  67.  
  68.     if(status & 0x1)
  69.         gpio->gpbdat = gpio->gpbdat & ~(0x1<<5); /*turn led 1 on*/
  70.     else
  71.         gpio->gpbdat = gpio->gpbdat | (0x1<<5); /*turn led 1 off*/
  72.  
  73.     if(status & (0x1<<1))
  74.         gpio->gpbdat = gpio->gpbdat & ~(0x1<<6); /*turn led 2 on*/
  75.     else
  76.         gpio->gpbdat = gpio->gpbdat | (0x1<<6); /*turn led 2 off*/
  77.  
  78.     if(status & (0x1<<2))
  79.         gpio->gpadat = gpio->gpadat & ~(0x1<<23); /* Turn on LED3 */
  80.     else
  81.         gpio->gpadat = gpio->gpadat | (0x1<<23); /* Turn off LED3 */
  82.  
  83.     if(status & (0x1<<3))
  84.         gpio->gpadat = gpio->gpadat & ~(0x1<<24); /* Turn on LED4 */
  85.     else
  86.         gpio->gpadat = gpio->gpadat | (0x1<<24); /* Turn off LED4 */
  87.  
  88. }
  89.  
  90. static inline void asm_delay(ulong loops)
  91. {
  92.     asm volatile ("1:\n" "subs %0, %1, #1\n"
  93.               "bne 1b" : "=r" (loops) : "0"(loops));
  94. }
  95.  
  96.  
  97. void display_value(int value)
  98. {
  99.  
  100.     display_status(15);
  101.     asm_delay(BLINK_INTERVAL);
  102.     display_status(0);
  103.     asm_delay(BLINK_INTERVAL);
  104.     display_status(value);
  105.     asm_delay(BLINK_INTERVAL);
  106.  
  107.     display_status(15);
  108.     asm_delay(BLINK_INTERVAL);
  109.     display_status(0);
  110.     asm_delay(BLINK_INTERVAL);
  111.     display_status(value >> 4);
  112.     asm_delay(BLINK_INTERVAL);
  113.  
  114.     display_status(15);
  115.     asm_delay(BLINK_INTERVAL);
  116.     display_status(0);
  117.     asm_delay(BLINK_INTERVAL);
  118.     display_status(value >> 8);
  119.     asm_delay(BLINK_INTERVAL);
  120.  
  121.     display_status(15);
  122.     asm_delay(BLINK_INTERVAL);
  123.     display_status(0);
  124.     asm_delay(BLINK_INTERVAL);
  125.     display_status(value >> 12);
  126.     asm_delay(BLINK_INTERVAL);
  127.  
  128.     display_status(15);
  129.     asm_delay(BLINK_INTERVAL);
  130.     display_status(0);
  131.     asm_delay(BLINK_INTERVAL);
  132.     display_status(value >> 16);
  133.     asm_delay(BLINK_INTERVAL);
  134.  
  135.     display_status(15);
  136.     asm_delay(BLINK_INTERVAL);
  137.     display_status(0);
  138.     asm_delay(BLINK_INTERVAL);
  139.     display_status(value >> 20);
  140.     asm_delay(BLINK_INTERVAL);
  141.  
  142.     display_status(15);
  143.     asm_delay(BLINK_INTERVAL);
  144.     display_status(0);
  145.     asm_delay(BLINK_INTERVAL);
  146.     display_status(value >> 24);
  147.     asm_delay(BLINK_INTERVAL);
  148.  
  149.     display_status(15);
  150.     asm_delay(BLINK_INTERVAL);
  151.     display_status(0);
  152.     asm_delay(BLINK_INTERVAL);
  153.     display_status(value >> 28);
  154.     asm_delay(BLINK_INTERVAL);
  155.     display_status(15);
  156.     asm_delay(BLINK_INTERVAL);
  157.  
  158. }
  159.  
  160.  
  161.  
  162.  
  163. static inline void watchdog_disable(void)
  164. {
  165.     struct s3c24xx_watchdog *const watchdog = s3c24xx_get_base_watchdog();
  166.  
  167.     watchdog->wtcon = 0;
  168.  
  169.     writel(WTCON_DISABLE_VAL, &watchdog->wtcon);
  170. }
  171.  
  172. static void pinmux_init(void)
  173. {
  174.     struct s3c24xx_gpio *const gpio = s3c24xx_get_base_gpio();
  175.  
  176.     /* LED1 -> GPB5, LED2 -> GPB6, LED3 -> GPA23. LED4 -> GPA24,
  177.      * GPIO 0 = led on, 1 = led off */
  178.  
  179.     /* set GPA23/24 to output */
  180.     gpio->gpacon = gpio->gpacon & ~(0x3<<23); /*configure GPA23 and GPA24 as output */
  181.  
  182.     /* set GPB5/6 to output and low */
  183.     /* bit 0, 3 and 4 are cleared to enable 0 = GPB6, 3 = GPB9, 4 = GPB10*/
  184.     gpio->gpbsel = gpio->gpbsel & ~(0x19<<0);
  185.  
  186.     /* set GPB5 and GPB6 to outputs */
  187.     gpio->gpbcon = gpio->gpbcon & ~(0xF<<10);
  188.     gpio->gpbcon = gpio->gpbcon | (0x5<<10);
  189.  
  190.     /* pull-up/down disable*/
  191.     gpio->gpbudp = gpio->gpbudp  & ~(0xF<<10);
  192.    
  193.     /* turn off all led */
  194.     display_status(0);
  195.  
  196.  
  197.  
  198.  
  199.     /* Init UART pins */
  200.     clrsetbits_le32(&gpio->gphcon, GPHCON_MASK(0) | GPHCON_MASK(1) |
  201.             GPHCON_MASK(2) | GPHCON_MASK(3) | GPHCON_MASK(4) |
  202.             GPHCON_MASK(5) | GPHCON_MASK(6) | GPHCON_MASK(7),
  203.             GPHCON_TXD(0) | GPHCON_RXD(0) | GPHCON_TXD(1) |
  204.             GPHCON_RXD(1) | GPHCON_TXD(2) | GPHCON_RXD(2) |
  205.             GPHCON_TXD(3) | GPHCON_RXD(3));
  206.            
  207.            
  208.     /* Init NAND interface */
  209.     setbits_le32(&gpio->gpacon, GPACON_CLE | GPACON_ALE | GPACON_NFWE |
  210.              GPACON_NFRE | GPACON_NRSTOUT | GPACON_NFCE);
  211.  
  212.  
  213. }
  214.  
  215. static void pll_init(void)
  216. {
  217.     struct s3c2416_sysctl *const sysctl = s3c2416_get_base_sysctl();
  218.  
  219.     /* Configure clocks division ratio */
  220.     clrsetbits_le32(&sysctl->clkdiv0,
  221.             CLKDIV0_ARMDIV_MASK | CLKDIV0_PREDIV_MASK |
  222.             CLKDIV0_HCLKDIV_MASK,
  223.             CLKDIV0_ARMDIV(ARMDIV) | CLKDIV0_PREDIV(PREDIV) |
  224.             CLKDIV0_HALFHCLK | CLKDIV0_PCLKDIV |
  225.             CLKDIV0_HCLKDIV(HCLKDIV));
  226.    
  227.  
  228.     /* Set MPLL lock time */
  229.     writel(M_LTIME, &sysctl->lockcon0);
  230.    
  231.     /* Configure MPLL */
  232.     writel(MPLLCON_MDIV(M_MDIV) | MPLLCON_PDIV(M_PDIV) |
  233.            PLLCON_SDIV(M_SDIV), &sysctl->mpllcon);
  234.        
  235.     /* Set EPLL lock time */
  236.     writel(E_LTIME, &sysctl->lockcon1);
  237.  
  238.     /* Configure EPLL */
  239.     writel(EPLLCON_MDIV(E_MDIV) | EPLLCON_PDIV(E_PDIV) |
  240.            PLLCON_SDIV(E_SDIV), &sysctl->epllcon);
  241.            
  242.  
  243.     /* MSYSCLK = MPLL and ESYSCLK = EPLL */
  244.     setbits_le32(&sysctl->clksrc,
  245.              CLKSRC_MSYSCLK_MPLL | CLKSRC_ESYSCLK_EPLL);
  246.  
  247.  
  248. }
  249.  
  250. static void dramctl_init(void)
  251. {
  252.     struct s3c24xx_dramctl *const dramctl = s3c24xx_get_base_dramctl();
  253.  
  254.     /* Step 1: Init BANKCFG & BANKCON1 */
  255.     writel(BANKCFG_VAL_DDR2, &dramctl->bankcfg);
  256.     writel(BANKCON1_VAL_DDR2, &dramctl->bankcon1);
  257.  
  258.  
  259.     /* Step 2: Init BANKCON2 */
  260.     writel(BANKCON2_VAL_DDR2, &dramctl->bankcon2);
  261.  
  262.     display_status(3);
  263.  
  264.     /* Step 3: Issue a PALL command */
  265.     writel(BANKCON1_VAL_DDR2 | BANKCON1_INIT_PALL, &dramctl->bankcon1);
  266.  
  267.     /* Step 4: Issue a EMRS2 command */
  268.     writel(BANKCON3_VAL_EMRS2, &dramctl->bankcon3);
  269.     writel(BANKCON1_VAL_DDR2 | BANKCON1_INIT_EMRS, &dramctl->bankcon1);
  270.  
  271.     /* Step 5: Issue a EMRS3 command */
  272.     writel(BANKCON3_VAL_EMRS3, &dramctl->bankcon3);
  273.     writel(BANKCON1_VAL_DDR2 | BANKCON1_INIT_EMRS, &dramctl->bankcon1);
  274.  
  275.     /* Step 6: Issue a EMRS1 command */
  276.     writel(BANKCON3_VAL_EMRS1, &dramctl->bankcon3);
  277.     writel(BANKCON1_VAL_DDR2 | BANKCON1_INIT_EMRS, &dramctl->bankcon1);
  278.  
  279.     /* Step 7: Issue a MRS command */
  280.     writel(BANKCON3_VAL_MRS | BANKCON3_MRS_DLL_RESET, &dramctl->bankcon3);
  281.     writel(BANKCON1_VAL_DDR2 | BANKCON1_INIT_MRS, &dramctl->bankcon1);
  282.  
  283.     /* Step 8: Issue a PALL command */
  284.     writel(BANKCON1_VAL_DDR2 | BANKCON1_INIT_PALL, &dramctl->bankcon1);
  285.  
  286.     /* Step 9: Write 0xFF into the refresh timer */
  287.     writel(0xFF, &dramctl->refresh);
  288.  
  289.     /* Step 10: Wait more than 120 clocks */
  290.     asm_delay(256);
  291.  
  292.     display_status(4);
  293.  
  294.     /* Step 11: Issue a MRS command */
  295.     writel(BANKCON3_VAL_MRS, &dramctl->bankcon3);
  296.     writel(BANKCON1_VAL_DDR2 | BANKCON1_INIT_MRS, &dramctl->bankcon1);
  297.  
  298.     /* Step 12: Issue a EMRS1 command */
  299.     writel(BANKCON3_VAL_EMRS1 | BANKCON3_EMRS1_OCD7 | BANKCON3_EMRS1_CAS3,
  300.            &dramctl->bankcon3);
  301.     writel(BANKCON1_VAL_DDR2 | BANKCON1_INIT_EMRS, &dramctl->bankcon1);
  302.  
  303.     writel(BANKCON3_VAL_EMRS1 | BANKCON3_EMRS1_CAS3, &dramctl->bankcon3);
  304.     writel(BANKCON1_VAL_DDR2 | BANKCON1_INIT_EMRS, &dramctl->bankcon1);
  305.  
  306.     /* Step 13: Write 0x87 into the refresh timer */
  307.     writel(0x87, &dramctl->refresh);
  308.  
  309.     display_status(5);
  310.  
  311.     /* Step 14: Normal Mode */
  312.     writel(BANKCON1_VAL_DDR2 | BANKCON1_INIT_NORMAL, &dramctl->bankcon1);
  313. }
  314.  
  315. #ifndef CONFIG_SPL_LIBCOMMON_SUPPORT
  316. #ifdef CONFIG_SPL_SERIAL_SUPPORT
  317. void puts(const char *str)
  318. {
  319.     serial_puts(str);
  320. }
  321. #else
  322. void puts(const char *str)
  323. {
  324. }
  325. #endif
  326. #endif
  327.  
  328. void board_init_f(ulong bootflag)
  329. {
  330.  
  331.     watchdog_disable();
  332.     pinmux_init();
  333.     pll_init();
  334.  
  335.     //display_value(0x87654321);
  336.  
  337.  
  338.     //display_status(6);
  339.  
  340.     // To here we can follow execution
  341.  
  342.     //serial_init_dev(0);
  343.  
  344.     preloader_console_init();
  345.     //display_status(2);
  346.     //puts("spl_board_init preloader_console_init\n");
  347.     //display_status(8);
  348.     dramctl_init();
  349.     //display_status(9);
  350.     //puts("spl_board_init dramctl_init\n");
  351.     display_status(10); // I get here if I don't do console_init();
  352.  
  353.  
  354. }
  355.  
  356. u32 spl_boot_device(void)
  357. {
  358. #ifdef CONFIG_SPL_NAND_SIMPLE
  359.  
  360.     /*puts("Loading U-Boot from NAND Flash...\n");*/
  361.     display_status(0);
  362.     while(1);
  363.     return BOOT_DEVICE_NAND;
  364. #else
  365.     /*puts("Unknown boot device\n");*/
  366.     hang();
  367. #endif
  368. }
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