test_Four_Bit_Counter.vhd

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-- Company:
-- Engineer:
--
-- Create Date: 08/24/2016 11:12:18 AM
-- Design Name:
-- Module Name: test_Four_Bit_Counter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
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-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity test_Four_Bit_Counter is
--  Port ( );
end test_Four_Bit_Counter;

architecture Behavioral of test_Four_Bit_Counter is

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT Four_Bit_Counter
    PORT(
         clk            : IN  std_logic;
         reset          : IN  std_logic;
         UP_DOWN        : IN  std_logic;
         LOAD           : IN  std_logic;
         TICK           : IN  std_logic;
         AUTO_MANUAL    : IN  std_logic;
         value          : IN  STD_LOGIC_VECTOR(0 to 3);
         Port_Counter   : OUT STD_LOGIC_VECTOR(0 to 3)
        );
    END COMPONENT;

    --Inputs
    signal clk          : std_logic := '0';
    signal reset        : std_logic := '0';
    signal UP_DOWN      : std_logic := '0';
    signal LOAD         : std_logic := '0';
    signal TICK         : std_logic := '0';
    signal AUTO_MANUAL  : std_logic := '0';
    signal value        : STD_LOGIC_VECTOR(0 to 3) := "0000";

    --Outputs
    signal Port_Counter : STD_LOGIC_VECTOR(0 to 3);

    -- Clock period definitions
    constant Port_Clk_period : time := 25 ns;

begin

    -- Instantiate the Unit Under Test (UUT)
    uut: Four_Bit_Counter PORT MAP (
          clk => clk,
          reset => reset,
          UP_DOWN => UP_DOWN,
          LOAD => LOAD,
          TICK => TICK,
          AUTO_MANUAL => AUTO_MANUAL,
          value => value,
          Port_Counter => Port_Counter
        );

   -- Clock process definitions
   Port_Clk_process :process
   begin
        clk <= '0';
        wait for Port_Clk_period/2;
        clk <= '1';
        wait for Port_Clk_period/2;
   end process;

    --Stimulus process
    stim_proc: process
    begin
        --hold reset state for 100ns
        wait for 100ns;
        reset <= '1';
        wait for 100ns;
        reset <= '0';
        wait for 100ns;
        --insert stimulus here
        AUTO_MANUAL <= '1';
        UP_DOWN <= '1';
        wait for 600ns;

        wait;
    end process;

end Behavioral;