moving_light.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity moving_light is
    --TO DO 1 -> deklarirati ulaz "clk" (STD_LOGIC) i izlaz "output" (STD_LOGIC_VECTOR) veličine 8 bita
    Port (
        clk: in STD_LOGIC;
            output: in STD_LOGIC_VECTOR(7 DOWNTO 0);
         );
end moving_light;

architecture Behavioral of moving_light is

    --TO DO 2 -> definirati korisnički tip podataka naziva "state" koji može imati vrijednosti "state0", ... "state7"
    TYPE state IS (state0, state1, state2, state3, state4, state5, state6, state7);
    --TO DO 3 -> deklarirati signale "current_state" i "next_state" koji su tipa "state"
    SIGNAL current_state, next_state: state;
    --TO DO 4 -> deklarirati signal "clk_div" koji je tipa STD_LOGIC
    SIGNAL clk_div: STD_LOGIC;

begin

    --TO DO 5 -> instancirati generički djelitelj frekvencije na način da od ulaznog singala takta kreira signal takta frekvencije 1 Hz


    ----Lower section of FSM----
    process(clk_div)
    begin
        --TO DO 6 -> na rastući brid signala takta "clk_div" signalu "current_state" pridružiti vrijednost signala "next_state"
        if(clk_div'EVENT AND clk_div='1' ) then
            current_state <= next_state;
        end if;
    end process;

    ----Upper section of FSM----
    process(current_state)
    begin
        case current_state is
            --TO DO 7 -> u ovisnosti o vrijednosti signala "current_state" signalima "output" i "next_state" pridružiti odgovarajuće vrijednosti
            when  state0 =>
                output <= "00000001";
                next_state <= state1;
            when  state1 =>
                output <= "00000010";
                next_state <= state2;
            when  state2=>
                output <= "00000100";
                next_state <= state3;
            when  state3=>
                output <= "00001000";
                next_state <= state4;
            when  state4=>
                output <= "00010000";
                next_state <= state5;
            when  state5=>
                output <= "00100000";
                next_state <= state6;
            when  state6=>
                output <= "01000000";
                next_state <= state7;
            when  state7=>
                output <= "10000000";
                next_state <= state0;
        end case;
    end process;

end Behavioral;