module bisma_arbiter(input_data,rst,clk,out);

parameter width =4 ,width_2 = 2;

input wire[width-1:0] input_data;
input wire rst,clk;
output reg[width-1:0] out;
reg [width_2-1:0]token,token_next = 0;


always@(posedge clk or posedge rst)
begin
	token <= token_next;
end

always@(input_data or rst)
begin

	if(token==0 && input_data == 4'bxxx1)
	begin
	out <= 4'b0001;
	token_next <= token_next + 1;
	end
	else if(token==1 && input_data == 4'bxx1x)
	begin
	out <= 4'b0010;
	token_next <= token_next+ 2;
	end
	else if(token==2 && input_data == 4'bx1xx)
	begin
	out <= 4'b0100;
	token_next <= token_next + 3;
	end
	else if(token==3 && input_data == 4'b1xxx)
	begin
	out <= 4'b1000;
	token_next <= token_next + 4;
	end
    else
	out <= 4'b0000;
end
endmodule

module bisma_allocator(input_data1,input_data2,input_data3,input_data4,out1,out2,out3,out4,clk,rst);
parameter width = 4;
input wire[width-1:0]input_data1,input_data2,input_data3,input_data4,out1,out2,out3,out4;
input wire clk,rst;

bisma_arbiter allocator1 (
.input_data(input_data1),
.clk(clk),
.rst(rst),
.out(out1)
);
bisma_arbiter allocator2 (
.input_data(input_data2),
.clk(clk),
.rst(rst),
.out(out2)
);
bisma_arbiter allocator3 (
.input_data(input_data3),
.clk(clk),
.rst(rst),
.out(out3)
);
bisma_arbiter allocator4 (
.input_data(input_data4),
.clk(clk),
.rst(rst),
.out(out4)
);

endmodule

`timescale 1ns / 1ns

module bisma_allocator_tb();
parameter width = 4;
reg [width-1:0] input_data1,input_data2,input_data3,input_data4;
reg clk,rst;
wire [width-1:0] out1,out2,out3,out4;

bisma_allocator allocator(
.input_data1(input_data1),
.input_data2(input_data2),
.input_data3(input_data3),
.input_data4(input_data4),
.out1(out1),
.out2(out2),
.out3(out3),
.out4(out4),
.clk(clk),
.rst(rst)
);


initial
begin
	clk = 0 ;
	rst = 0 ;
	input_data1 = 0;
	#5
	input_data1 = 4'b0001;
	#20
	input_data2 = 4'b0011;
	#20
	input_data3 = 4'b0101;
	#20
	input_data4 = 4'b1001;

end
always
#10 clk = !clk;
endmodule