Part 4 Test

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:   00:01:45 02/01/2015
// Design Name:   multiply
// Module Name:   C:/Users/rbridges/Desktop/CSE 140L/Lab2Part4/multiplyTest.v
// Project Name:  Lab2Part4
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: multiply
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////

module multiplyTest;

    reg [3:0]a;
    reg [3:0]b;
    reg clock;
    // Outputs
    wire [7:0] p;

    // Instantiate the Unit Under Test (UUT)
    multiply uut (
        .p(p),
        .a(a),
        .b(b),
        .clock(clock)
    );

    initial begin

        clock = 0;
        //pos + pos
        #50;
        clock = 1'b1;
        a = 8'b0101;
        b = 8'b1101;
       //     01100010

        #50;
        clock = 0;
        //pos + neg
        #50
        clock = 1'b1;
        a = 8'b1111;
        b = 8'b1100;
        //     00000011

        #50;
        clock = 0;
        //neg + pos
        #50
        clock = 1'b1;
        a = 8'b1100;
        b = 8'b0101;
        //     00000001

        #50;
        clock = 0;
        //neg + neg
        #50
        clock = 1'b1;
        a = 8'b1011;
        b = 8'b1110;
        //     10011100

        #50;
        clock = 0;
        //pos - pos
        #50
        clock = 1'b1;
        a = 8'b0101;
        b = 8'b0010;
        //     00101011

        #50;
        clock = 0;
        //pos - neg
        #50
        clock = 1'b1;
        a = 8'b0101;
        b = 8'b1110;
        //     01101001

        #50;
        clock = 0;
        //neg - pos
        #50
        clock = 1'b1;
        a = 8'b1110;
        b = 8'b0011;
        //     10111011

        #50;
        clock = 0;
        //neg - neg
        #50
        clock = 1'b1;
        a = 8'b1011;
        b = 8'b1100;
        //     11101101


        #50;
        clock = 0;
        //overflow pos + pos
        #50
        clock = 1'b1;
        a = 8'b0000;
        b = 8'b0000;

        #50;
        clock = 0;
        //overflow neg + neg
        #50
        clock = 1'b1;
        a = 8'b0011;
        b = 8'b1011;

    end

endmodule