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- ----------------------------------------------------------------------------------
- -- Company:
- -- Engineer:
- --
- -- Create Date: 22:06:10 12/03/2014
- -- Design Name:
- -- Module Name: MainModule - Behavioral
- -- Project Name:
- -- Target Devices:
- -- Tool versions:
- -- Description:
- --
- -- Dependencies:
- --
- -- Revision:
- -- Revision 0.01 - File Created
- -- Additional Comments:
- --
- ----------------------------------------------------------------------------------
- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
- use IEEE.STD_LOGIC_UNSIGNED.ALL;
- -- Uncomment the following library declaration if using
- -- arithmetic functions with Signed or Unsigned values
- --use IEEE.NUMERIC_STD.ALL;
- -- Uncomment the following library declaration if instantiating
- -- any Xilinx primitives in this code.
- --library UNISIM;
- --use UNISIM.VComponents.all;
- entity MainModule is
- Port ( iCLK : in STD_LOGIC;
- inRST : in STD_LOGIC;
- inLEFT : in STD_LOGIC;
- inRIGHT : in STD_LOGIC;
- inHAZ : in STD_LOGIC;
- oLEFT : out STD_LOGIC_VECTOR (2 downto 0);
- oRIGHT : out STD_LOGIC_VECTOR (2 downto 0)
- );
- end MainModule;
- architecture Behavioral of MainModule is
- type tSTATES is (IDLE, L1, L2, L3, R1, R2, R3, LR3);
- signal sSTATE: tSTATES;
- signal sDEVIDER: STD_LOGIC_VECTOR(23 downto 0);
- signal sENABLE_CS: STD_LOGIC;
- constant cDEVIDER_END: integer := 12;
- signal sPWM_DEVIDER: STD_LOGIC_VECTOR(2 downto 0);
- signal sPWM_CLOCK: STD_LOGIC;
- type tPWM_STATES is (P25, P50, P75);
- signal sPWM_STATE: tPWM_STATES;
- signal sLEFT, sRIGHT: STD_LOGIC_VECTOR(2 downto 0);
- begin
- -- Proces u kome je realizovan automat, sa asihronim resetom
- Automat: process (iCLK, inRST) begin
- if (inRST = '0') then
- sSTATE <= IDLE;
- elsif (rising_edge(iCLK)) then
- if (sENABLE_CS = '1') then
- case (sSTATE) is
- when IDLE =>
- if (inHAZ = '0') then
- sSTATE <= LR3;
- elsif (inLEFT = '0' and inRIGHT = '0') then
- sSTATE <= LR3;
- elsif (inLEFT = '0') then
- sSTATE <= L1;
- elsif (inRIGHT = '0') then
- sSTATE <= R1;
- else
- sSTATE <= IDLE;
- end if;
- when L1 => sSTATE <= L2;
- when L2 => sSTATE <= L3;
- when L3 => sSTATE <= IDLE;
- when R1 => sSTATE <= R2;
- when R2 => sSTATE <= R3;
- when R3 => sSTATE <= IDLE;
- when LR3 => sSTATE <= IDLE;
- --when others => sSTATE <= IDLE;
- end case;
- end if;
- end if;
- end process;
- -- Binarni djelitelj
- -- 12*10^6 = 2^x; log_2(12*10^6) = x; x = 24
- Divider: process (iCLK, inRST) begin
- if (inRST = '0') then
- sDEVIDER <= (others => '0');
- sENABLE_CS <= '0';
- elsif (rising_edge(iCLK)) then
- if (sDEVIDER = cDEVIDER_END) then
- sDEVIDER <= (others => '0');
- sENABLE_CS <= '1';
- else
- sENABLE_CS <= '0';
- sDEVIDER <= sDEVIDER + 1;
- end if;
- end if;
- end process;
- PWMClock: process(iCLK, inRST) begin
- if (inRST = '0') then
- sPWM_DEVIDER <= (others => '0');
- sPWM_STATE <= P25;
- sPWM_CLOCK <= '0';
- elsif (rising_edge(iCLK)) then
- -- 75%
- if (sPWM_STATE = P75) then
- if (sPWM_DEVIDER = 0) then
- sPWM_CLOCK <= '1';
- end if;
- if (sPWM_DEVIDER = 2) then
- sPWM_DEVIDER <= (others => '0');
- sPWM_CLOCK <= '0';
- else
- sPWM_DEVIDER <= sPWM_DEVIDER + 1;
- end if;
- -- 25%
- elsif (sPWM_STATE = P25) then
- if (sPWM_DEVIDER = 0) then
- sPWM_CLOCK <= '0';
- end if;
- if (sPWM_DEVIDER = 2) then
- sPWM_DEVIDER <= (others => '0');
- sPWM_CLOCK <= '1';
- else
- sPWM_DEVIDER <= sPWM_DEVIDER + 1;
- end if;
- -- 50%
- elsif (sPWM_STATE = P50) then
- sPWM_CLOCK <= not sPWM_CLOCK;
- end if;
- end if;
- end process;
- PWMApply: process (sLEFT, sPWM_CLOCK) begin
- if (sLEFT(0) = '1') then
- oLEFT(0) <= sPWM_CLOCK;
- else oLEFT(0) <= '0'; end if;
- if (sLEFT(1) = '1') then
- oLEFT(1) <= sPWM_CLOCK;
- else oLEFT(1) <= '0'; end if;
- if (sLEFT(2) = '1') then
- oLEFT(2) <= sPWM_CLOCK;
- else oLEFT(2) <= '0'; end if;
- end process;
- -- Dodjela ukljucivanje dioda zavisno od stanja
- sLEFT <= "000" when sSTATE = IDLE else
- "001" when sSTATE = L1 else
- "011" when sSTATE = L2 else
- "111" when sSTATE = L3 else
- "111" when sSTATE = LR3 else
- "000"; -- R1, R2, R3
- sRIGHT <= "000" when sSTATE = IDLE else
- "100" when sSTATE = R1 else
- "110" when sSTATE = R2 else
- "111" when sSTATE = R3 else
- "111" when sSTATE = LR3 else
- "000"; -- L1, L2, L3
- end Behavioral;
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