library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ram is
    generic(
        M : integer := 4;
        N : integer := 3;
        X : integer := 10
    );
    port(
        rd_in   : in    std_logic;
        wr_in   : in    std_logic;
        clk     : in    std_logic;
        rst     : in    std_logic;
        addr_in : in    std_logic_vector(M - 1 downto 0);
        finish  : out   std_logic;
        data    : inout std_logic_vector(N - 1 downto 0)
    );
end entity ram;

architecture RTL of ram is
    type mem_type is array (0 to 2 ** M - 1) of std_logic_vector(N - 1 downto 0);
    signal count : integer := X;
    signal mem     : mem_type;

begin
    process(clk, rst) is


    begin
        if rst = '1' then
            count <= X;
        elsif rising_edge(clk) then
            if (rd_in = '1' or wr_in = '1') then
                count <= count - 1;
                if (count = 0) then
                    count <= X;
                end if;
            end if;
        end if;

    end process;

    process (clk) is
    begin
        if(count = 0) then
            if(wr_in = '1') then
                mem(to_integer(unsigned(addr_in))) <= data;

            end if;
        end if;
    end process;


    process (rd_in, count, wr_in) is
    begin
        if(count = 0) then
            if(rd_in = '1') then
                data <= mem(to_integer(unsigned(addr_in)));
            elsif(wr_in = '1') then
                data <= (others => 'Z');
            end if;
       else
            data <= (others => 'Z');

        end if;
    end process;
    finish <= '1' when count = 0 else '0';


end architecture RTL;