entity BReg is
port (
        clk : in std_logic;
        reset : in std_logic;
        RA : in std_logic_vector (4 downto 0);
        RB : in std_logic_vector (4 downto 0);
        RW : in std_logic_vector (4 downto 0);
        BusW : in std_logic_vector (31 downto 0)
        BusW2 : in std_logic_vector (31 downto 0);
        RegWrite : in std_logic;
        BusA : out std_logic_vector (31 downto 0);
        BusB : out std_logic_vector (31 downto 0)
    );
end BReg;

architecture Behavioral of BReg is
    type reg_array is array (0 to 31) of std_logic_vector(31 downto 0);
    signal reg_file : reg_array;

    begin
     process(clk)
        begin
            if (clk'event and clk='0') then
                if reset='1' then
                    for i in 0 to 31 loop
                        reg_file(i) <= "00000000000000000000000000000000";
                     end loop;
                else
                    if RegWrite = '1' then
                         reg_file(conv_integer(RW)) <= BusW;
                    end if;
                end if;
            end if;
    end process;

    --get data stored at register RA
    BusA <= reg_file(conv_integer(RA));
    --get data stored at register RB
    BusB <= reg_file(conv_integer(RB));


end Behavioral;