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  1. fFrom b56f56d1569be98fc3f8e4a298e8101ce791c98c Mon Sep 17 00:00:00 2001
  2. From: root <aneox.inbox@gmail.com>
  3. Date: Wed, 28 Dec 2016 03:18:14 +0600
  4. Subject: [PATCH 1/2] apb1 clock can be changed in script.bin
  5.  
  6. ---
  7. arch/arm/mach-sun7i/clock/clock.c | 22 ++++++++++++++++++++++
  8. arch/arm/mach-sun7i/clock/sys_clk.c | 2 ++
  9. drivers/tty/serial/8250/8250_sunxi.c | 4 ++--
  10. 3 files changed, 26 insertions(+), 2 deletions(-)
  11.  
  12. diff --git a/arch/arm/mach-sun7i/clock/clock.c b/arch/arm/mach-sun7i/clock/clock.c
  13. index 26fe462..9fd2ab9 100644
  14. --- a/arch/arm/mach-sun7i/clock/clock.c
  15. +++ b/arch/arm/mach-sun7i/clock/clock.c
  16. @@ -126,6 +126,28 @@ int clk_init(void)
  17. }
  18. }
  19.  
  20. + if (script_parser_fetch("clock", "apb1", &val, sizeof(int)) == 0) {
  21. + struct clk *tmpClk;
  22. + __u32 tmpRate, min, max;
  23. + CCU_INF("script config apb1 to %dMHz\n", val);
  24. + clk = &aw_clock[AW_SYS_CLK_APB1];
  25. + tmpClk = &aw_clock[AW_SYS_CLK_PLL62];
  26. + CCU_INF("apb1 0 clock was %lu\n", clk_get_rate(clk));
  27. + clk_set_parent(clk, tmpClk);
  28. + tmpRate = clk_get_rate(tmpClk) / 1000000;
  29. + CCU_INF("apb1 new parent clock is %lu\n", clk_get_rate(clk_get_parent(clk)));
  30. + min = (tmpRate / (8 * 32));
  31. + max = tmpRate;
  32. + if (val >= min && val <= max) {
  33. + clk_enable(clk);
  34. + clk_set_rate(clk, val * 1000000);
  35. + CCU_INF("apb1 new clock is %lu\n", clk_get_rate(clk));
  36. + } else {
  37. + CCU_ERR(" invalid apb1 value, must in %dMHz ~ %dGHz\n", min, max);
  38. + }
  39. + }
  40. +
  41. +
  42. return 0;
  43. }
  44. arch_initcall(clk_init);
  45. diff --git a/arch/arm/mach-sun7i/clock/sys_clk.c b/arch/arm/mach-sun7i/clock/sys_clk.c
  46. index 0928935..8658a30 100644
  47. --- a/arch/arm/mach-sun7i/clock/sys_clk.c
  48. +++ b/arch/arm/mach-sun7i/clock/sys_clk.c
  49. @@ -903,6 +903,8 @@ static int sys_clk_set_rate(__aw_ccu_clk_id_e id, __u64 rate)
  50. aw_ccu_reg->Apb1ClkDiv.PreDiv = tmpDivP;
  51. aw_ccu_reg->Apb1ClkDiv.ClkDiv = tmpDivM;
  52.  
  53. + CCU_INF("apb1 new config preDiv %d ClkDiv %d\n", tmpDivP, tmpDivM);
  54. +
  55. return 0;
  56. }
  57. default: {
  58. diff --git a/drivers/tty/serial/8250/8250_sunxi.c b/drivers/tty/serial/8250/8250_sunxi.c
  59. index 25fdcff..17560d3 100644
  60. --- a/drivers/tty/serial/8250/8250_sunxi.c
  61. +++ b/drivers/tty/serial/8250/8250_sunxi.c
  62. @@ -212,8 +212,8 @@ static int __devinit sw_serial_probe(struct platform_device *dev)
  63. port.serial_out = sw_serial_out32;
  64. port.handle_irq = sw_serial_handle_irq;
  65.  
  66. - pr_info("serial probe %d irq %d mapbase 0x%08x\n", dev->id,
  67. - sport->irq, sport->mmres->start);
  68. + pr_info("serial probe %d irq %d mapbase 0x%08x uartclk %u\n", dev->id,
  69. + sport->irq, sport->mmres->start, port.uartclk);
  70. ret = serial8250_register_port(&port);
  71. if (ret < 0)
  72. goto free_dev;
  73. --
  74. 2.1.4
  75.  
  76.  
  77. From d3da6a98f8e299caa4dacfd82307f693babbc1a7 Mon Sep 17 00:00:00 2001
  78. From: AneoX <aneox.inbox@gmail.com>
  79. Date: Sun, 8 Jan 2017 06:35:04 +0600
  80. Subject: [PATCH 2/2] apb1 pll6 parent fix
  81.  
  82. ---
  83. arch/arm/mach-sun7i/clock/clock.c | 2 +-
  84. arch/arm/mach-sun7i/clock/sys_clk.c | 6 +++---
  85. 2 files changed, 4 insertions(+), 4 deletions(-)
  86.  
  87. diff --git a/arch/arm/mach-sun7i/clock/clock.c b/arch/arm/mach-sun7i/clock/clock.c
  88. index 9fd2ab9..9e07969 100644
  89. --- a/arch/arm/mach-sun7i/clock/clock.c
  90. +++ b/arch/arm/mach-sun7i/clock/clock.c
  91. @@ -131,7 +131,7 @@ int clk_init(void)
  92. __u32 tmpRate, min, max;
  93. CCU_INF("script config apb1 to %dMHz\n", val);
  94. clk = &aw_clock[AW_SYS_CLK_APB1];
  95. - tmpClk = &aw_clock[AW_SYS_CLK_PLL62];
  96. + tmpClk = &aw_clock[AW_SYS_CLK_PLL6];
  97. CCU_INF("apb1 0 clock was %lu\n", clk_get_rate(clk));
  98. clk_set_parent(clk, tmpClk);
  99. tmpRate = clk_get_rate(tmpClk) / 1000000;
  100. diff --git a/arch/arm/mach-sun7i/clock/sys_clk.c b/arch/arm/mach-sun7i/clock/sys_clk.c
  101. index 8658a30..e055c03 100644
  102. --- a/arch/arm/mach-sun7i/clock/sys_clk.c
  103. +++ b/arch/arm/mach-sun7i/clock/sys_clk.c
  104. @@ -84,7 +84,7 @@ static __aw_ccu_clk_id_e sys_clk_get_parent(__aw_ccu_clk_id_e id)
  105. case 0:
  106. return AW_SYS_CLK_HOSC;
  107. case 1:
  108. - return AW_SYS_CLK_PLL62;
  109. + return AW_SYS_CLK_PLL6;
  110. case 2:
  111. return AW_SYS_CLK_LOSC;
  112. case 3:
  113. @@ -313,7 +313,7 @@ static __u64 sys_clk_get_rate(__aw_ccu_clk_id_e id)
  114. tmpApb1Rate = 24000000;
  115. break;
  116. case 1:
  117. - tmpApb1Rate = sys_clk_get_rate(AW_SYS_CLK_PLL62);
  118. + tmpApb1Rate = sys_clk_get_rate(AW_SYS_CLK_PLL6);
  119. break;
  120. case 2:
  121. tmpApb1Rate = 32768;
  122. @@ -403,7 +403,7 @@ static __s32 sys_clk_set_parent(__aw_ccu_clk_id_e id, __aw_ccu_clk_id_e parent)
  123. case AW_SYS_CLK_HOSC:
  124. aw_ccu_reg->Apb1ClkDiv.ClkSrc = 0;
  125. break;
  126. - case AW_SYS_CLK_PLL62:
  127. + case AW_SYS_CLK_PLL6:
  128. aw_ccu_reg->Apb1ClkDiv.ClkSrc = 1;
  129. break;
  130. default:
  131. --
  132. 2.1.4
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