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  1. /*
  2.  * ar8216.c: AR8216 switch driver
  3.  *
  4.  * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
  5.  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
  6.  *
  7.  * This program is free software; you can redistribute it and/or
  8.  * modify it under the terms of the GNU General Public License
  9.  * as published by the Free Software Foundation; either version 2
  10.  * of the License, or (at your option) any later version.
  11.  *
  12.  * This program is distributed in the hope that it will be useful,
  13.  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15.  * GNU General Public License for more details.
  16.  */
  17.  
  18. #include <linux/if.h>
  19. #include <linux/module.h>
  20. #include <linux/init.h>
  21. #include <linux/list.h>
  22. #include <linux/if_ether.h>
  23. #include <linux/skbuff.h>
  24. #include <linux/netdevice.h>
  25. #include <linux/netlink.h>
  26. #include <linux/bitops.h>
  27. #include <net/genetlink.h>
  28. #include <linux/switch.h>
  29. #include <linux/delay.h>
  30. #include <linux/phy.h>
  31. #include <linux/netdevice.h>
  32. #include <linux/etherdevice.h>
  33. #include <linux/lockdep.h>
  34. #include <linux/ar8216_platform.h>
  35. #include <linux/workqueue.h>
  36. #include <linux/of_device.h>
  37.  
  38. #include "ar8216.h"
  39.  
  40. /* size of the vlan table */
  41. #define AR8X16_MAX_VLANS    128
  42. #define AR8X16_PROBE_RETRIES    10
  43. #define AR8X16_MAX_PORTS    8
  44.  
  45. #define AR8XXX_MIB_WORK_DELAY   2000 /* msecs */
  46.  
  47. struct ar8xxx_priv;
  48.  
  49. #define AR8XXX_CAP_GIGE         BIT(0)
  50. #define AR8XXX_CAP_MIB_COUNTERS     BIT(1)
  51.  
  52. enum {
  53.     AR8XXX_VER_AR8216 = 0x01,
  54.     AR8XXX_VER_AR8236 = 0x03,
  55.     AR8XXX_VER_AR8316 = 0x10,
  56.     AR8XXX_VER_AR8327 = 0x12,
  57.     AR8XXX_VER_AR8337 = 0x13,
  58. };
  59.  
  60. struct ar8xxx_mib_desc {
  61.     unsigned int size;
  62.     unsigned int offset;
  63.     const char *name;
  64. };
  65.  
  66. struct ar8xxx_chip {
  67.     unsigned long caps;
  68.  
  69.     int (*hw_init)(struct ar8xxx_priv *priv);
  70.     void (*init_globals)(struct ar8xxx_priv *priv);
  71.     void (*init_port)(struct ar8xxx_priv *priv, int port);
  72.     void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 members);
  73.     u32 (*read_port_status)(struct ar8xxx_priv *priv, int port);
  74.     int (*atu_flush)(struct ar8xxx_priv *priv);
  75.     void (*vtu_flush)(struct ar8xxx_priv *priv);
  76.     void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vlan);
  77.  
  78.     const struct ar8xxx_mib_desc *mib_decs;
  79.     unsigned num_mibs;
  80. };
  81.  
  82. struct ar8216_data {
  83.     u8 vlan_tagged;
  84. };
  85.  
  86. struct ar8327_data {
  87.     u8 vlan_tagged[AR8X16_MAX_VLANS];
  88.     u32 port0_status;
  89.     u32 port6_status;
  90. };
  91.  
  92. struct ar8xxx_priv {
  93.     struct switch_dev dev;
  94.     struct mii_bus *mii_bus;
  95.     struct phy_device *phy;
  96.  
  97.     u32 (*read)(struct ar8xxx_priv *priv, int reg);
  98.     void (*write)(struct ar8xxx_priv *priv, int reg, u32 val);
  99.  
  100.     int (*get_port_link)(unsigned port);
  101.  
  102.     const struct net_device_ops *ndo_old;
  103.     struct net_device_ops ndo;
  104.     struct mutex reg_mutex;
  105.     u8 chip_ver;
  106.     u8 chip_rev;
  107.     const struct ar8xxx_chip *chip;
  108.     union {
  109.         struct ar8216_data ar8216;
  110.         struct ar8327_data ar8327;
  111.     } chip_data;
  112.     bool initialized;
  113.     bool port4_phy;
  114.     char buf[2048];
  115.  
  116.     bool init;
  117.     bool mii_lo_first;
  118.  
  119.     struct mutex mib_lock;
  120.     struct delayed_work mib_work;
  121.     int mib_next_port;
  122.     u64 *mib_stats;
  123.  
  124.     struct list_head list;
  125.     unsigned int use_count;
  126.  
  127.     /* all fields below are cleared on reset */
  128.     bool vlan;
  129.     u16 vlan_id[AR8X16_MAX_VLANS];
  130.     u8 vlan_table[AR8X16_MAX_VLANS];
  131.     u16 pvid[AR8X16_MAX_PORTS];
  132.  
  133.     /* mirroring */
  134.     bool mirror_rx;
  135.     bool mirror_tx;
  136.     int source_port;
  137.     int monitor_port;
  138. };
  139.  
  140. #define MIB_DESC(_s , _o, _n)   \
  141.     {           \
  142.         .size = (_s),   \
  143.         .offset = (_o), \
  144.         .name = (_n),   \
  145.     }
  146.  
  147. static const struct ar8xxx_mib_desc ar8216_mibs[] = {
  148.     MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
  149.     MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
  150.     MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
  151.     MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
  152.     MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
  153.     MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
  154.     MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
  155.     MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
  156.     MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
  157.     MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
  158.     MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
  159.     MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
  160.     MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
  161.     MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
  162.     MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
  163.     MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
  164.     MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
  165.     MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
  166.     MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
  167.     MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
  168.     MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
  169.     MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
  170.     MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
  171.     MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
  172.     MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
  173.     MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
  174.     MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
  175.     MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
  176.     MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
  177.     MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
  178.     MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
  179.     MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
  180.     MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
  181.     MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
  182.     MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
  183.     MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
  184.     MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
  185. };
  186.  
  187. static const struct ar8xxx_mib_desc ar8236_mibs[] = {
  188.     MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
  189.     MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
  190.     MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
  191.     MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
  192.     MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
  193.     MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
  194.     MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
  195.     MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
  196.     MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
  197.     MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
  198.     MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
  199.     MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
  200.     MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
  201.     MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
  202.     MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
  203.     MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
  204.     MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
  205.     MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
  206.     MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
  207.     MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
  208.     MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
  209.     MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
  210.     MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
  211.     MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
  212.     MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
  213.     MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
  214.     MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
  215.     MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
  216.     MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
  217.     MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
  218.     MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
  219.     MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
  220.     MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
  221.     MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
  222.     MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
  223.     MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
  224.     MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
  225.     MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
  226.     MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
  227. };
  228.  
  229. static DEFINE_MUTEX(ar8xxx_dev_list_lock);
  230. static LIST_HEAD(ar8xxx_dev_list);
  231.  
  232. static inline struct ar8xxx_priv *
  233. swdev_to_ar8xxx(struct switch_dev *swdev)
  234. {
  235.     return container_of(swdev, struct ar8xxx_priv, dev);
  236. }
  237.  
  238. static inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv)
  239. {
  240.     return priv->chip->caps & AR8XXX_CAP_GIGE;
  241. }
  242.  
  243. static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv)
  244. {
  245.     return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
  246. }
  247.  
  248. static inline bool chip_is_ar8216(struct ar8xxx_priv *priv)
  249. {
  250.     return priv->chip_ver == AR8XXX_VER_AR8216;
  251. }
  252.  
  253. static inline bool chip_is_ar8236(struct ar8xxx_priv *priv)
  254. {
  255.     return priv->chip_ver == AR8XXX_VER_AR8236;
  256. }
  257.  
  258. static inline bool chip_is_ar8316(struct ar8xxx_priv *priv)
  259. {
  260.     return priv->chip_ver == AR8XXX_VER_AR8316;
  261. }
  262.  
  263. static inline bool chip_is_ar8327(struct ar8xxx_priv *priv)
  264. {
  265.     return priv->chip_ver == AR8XXX_VER_AR8327;
  266. }
  267.  
  268. static inline bool chip_is_ar8337(struct ar8xxx_priv *priv)
  269. {
  270.     return priv->chip_ver == AR8XXX_VER_AR8337;
  271. }
  272.  
  273. static inline void
  274. split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
  275. {
  276.     regaddr >>= 1;
  277.     *r1 = regaddr & 0x1e;
  278.  
  279.     regaddr >>= 5;
  280.     *r2 = regaddr & 0x7;
  281.  
  282.     regaddr >>= 3;
  283.     *page = regaddr & 0x1ff;
  284. }
  285.  
  286. static u32
  287. ar8xxx_mii_read(struct ar8xxx_priv *priv, int reg)
  288. {
  289.     struct mii_bus *bus = priv->mii_bus;
  290.     u16 r1, r2, page;
  291.     u16 lo, hi;
  292.  
  293.     split_addr((u32) reg, &r1, &r2, &page);
  294.  
  295.     mutex_lock(&bus->mdio_lock);
  296.  
  297.     bus->write(bus, 0x18, 0, page);
  298.     usleep_range(1000, 2000); /* wait for the page switch to propagate */
  299.     lo = bus->read(bus, 0x10 | r2, r1);
  300.     hi = bus->read(bus, 0x10 | r2, r1 + 1);
  301.  
  302.     mutex_unlock(&bus->mdio_lock);
  303.  
  304.     return (hi << 16) | lo;
  305. }
  306.  
  307. static void
  308. ar8xxx_mii_write(struct ar8xxx_priv *priv, int reg, u32 val)
  309. {
  310.     struct mii_bus *bus = priv->mii_bus;
  311.     u16 r1, r2, r3;
  312.     u16 lo, hi;
  313.  
  314.     split_addr((u32) reg, &r1, &r2, &r3);
  315.     lo = val & 0xffff;
  316.     hi = (u16) (val >> 16);
  317.  
  318.     mutex_lock(&bus->mdio_lock);
  319.  
  320.     bus->write(bus, 0x18, 0, r3);
  321.     usleep_range(1000, 2000); /* wait for the page switch to propagate */
  322.     if (priv->mii_lo_first) {
  323.         bus->write(bus, 0x10 | r2, r1, lo);
  324.         bus->write(bus, 0x10 | r2, r1 + 1, hi);
  325.     } else {
  326.         bus->write(bus, 0x10 | r2, r1 + 1, hi);
  327.         bus->write(bus, 0x10 | r2, r1, lo);
  328.     }
  329.  
  330.     mutex_unlock(&bus->mdio_lock);
  331. }
  332.  
  333. static void
  334. ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
  335.              u16 dbg_addr, u16 dbg_data)
  336. {
  337.     struct mii_bus *bus = priv->mii_bus;
  338.  
  339.     mutex_lock(&bus->mdio_lock);
  340.     bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
  341.     bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
  342.     mutex_unlock(&bus->mdio_lock);
  343. }
  344.  
  345. static void
  346. ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
  347. {
  348.     struct mii_bus *bus = priv->mii_bus;
  349.  
  350.     mutex_lock(&bus->mdio_lock);
  351.     bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
  352.     bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
  353.     mutex_unlock(&bus->mdio_lock);
  354. }
  355.  
  356. static u32
  357. ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
  358. {
  359.     u32 v;
  360.  
  361.     lockdep_assert_held(&priv->reg_mutex);
  362.  
  363.     v = priv->read(priv, reg);
  364.     v &= ~mask;
  365.     v |= val;
  366.     priv->write(priv, reg, v);
  367.  
  368.     return v;
  369. }
  370.  
  371. static inline void
  372. ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val)
  373. {
  374.     u32 v;
  375.  
  376.     lockdep_assert_held(&priv->reg_mutex);
  377.  
  378.     v = priv->read(priv, reg);
  379.     v |= val;
  380.     priv->write(priv, reg, v);
  381. }
  382.  
  383. static int
  384. ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
  385.         unsigned timeout)
  386. {
  387.     int i;
  388.  
  389.     for (i = 0; i < timeout; i++) {
  390.         u32 t;
  391.  
  392.         t = priv->read(priv, reg);
  393.         if ((t & mask) == val)
  394.             return 0;
  395.  
  396.         usleep_range(1000, 2000);
  397.     }
  398.  
  399.     return -ETIMEDOUT;
  400. }
  401.  
  402. static int
  403. ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
  404. {
  405.     unsigned mib_func;
  406.     int ret;
  407.  
  408.     lockdep_assert_held(&priv->mib_lock);
  409.  
  410.     if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
  411.         mib_func = AR8327_REG_MIB_FUNC;
  412.     else
  413.         mib_func = AR8216_REG_MIB_FUNC;
  414.  
  415.     mutex_lock(&priv->reg_mutex);
  416.     /* Capture the hardware statistics for all ports */
  417.     ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
  418.     mutex_unlock(&priv->reg_mutex);
  419.  
  420.     /* Wait for the capturing to complete. */
  421.     ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
  422.     if (ret)
  423.         goto out;
  424.  
  425.     ret = 0;
  426.  
  427. out:
  428.     return ret;
  429. }
  430.  
  431. static int
  432. ar8xxx_mib_capture(struct ar8xxx_priv *priv)
  433. {
  434.     return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
  435. }
  436.  
  437. static int
  438. ar8xxx_mib_flush(struct ar8xxx_priv *priv)
  439. {
  440.     return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
  441. }
  442.  
  443. static void
  444. ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
  445. {
  446.     unsigned int base;
  447.     u64 *mib_stats;
  448.     int i;
  449.  
  450.     WARN_ON(port >= priv->dev.ports);
  451.  
  452.     lockdep_assert_held(&priv->mib_lock);
  453.  
  454.     if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
  455.         base = AR8327_REG_PORT_STATS_BASE(port);
  456.     else if (chip_is_ar8236(priv) ||
  457.          chip_is_ar8316(priv))
  458.         base = AR8236_REG_PORT_STATS_BASE(port);
  459.     else
  460.         base = AR8216_REG_PORT_STATS_BASE(port);
  461.  
  462.     mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
  463.     for (i = 0; i < priv->chip->num_mibs; i++) {
  464.         const struct ar8xxx_mib_desc *mib;
  465.         u64 t;
  466.  
  467.         mib = &priv->chip->mib_decs[i];
  468.         t = priv->read(priv, base + mib->offset);
  469.         if (mib->size == 2) {
  470.             u64 hi;
  471.  
  472.             hi = priv->read(priv, base + mib->offset + 4);
  473.             t |= hi << 32;
  474.         }
  475.  
  476.         if (flush)
  477.             mib_stats[i] = 0;
  478.         else
  479.             mib_stats[i] += t;
  480.     }
  481. }
  482.  
  483. static void
  484. ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
  485.               struct switch_port_link *link)
  486. {
  487.     u32 status;
  488.     u32 speed;
  489.  
  490.     memset(link, '\0', sizeof(*link));
  491.  
  492.     status = priv->chip->read_port_status(priv, port);
  493.  
  494.     link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
  495.     if (link->aneg) {
  496.         link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
  497.     } else {
  498.         link->link = true;
  499.  
  500.         if (priv->get_port_link) {
  501.             int err;
  502.  
  503.             err = priv->get_port_link(port);
  504.             if (err >= 0)
  505.                 link->link = !!err;
  506.         }
  507.     }
  508.  
  509.     if (!link->link)
  510.         return;
  511.  
  512.     link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
  513.     link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
  514.     link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
  515.  
  516.     speed = (status & AR8216_PORT_STATUS_SPEED) >>
  517.          AR8216_PORT_STATUS_SPEED_S;
  518.  
  519.     switch (speed) {
  520.     case AR8216_PORT_SPEED_10M:
  521.         link->speed = SWITCH_PORT_SPEED_10;
  522.         break;
  523.     case AR8216_PORT_SPEED_100M:
  524.         link->speed = SWITCH_PORT_SPEED_100;
  525.         break;
  526.     case AR8216_PORT_SPEED_1000M:
  527.         link->speed = SWITCH_PORT_SPEED_1000;
  528.         break;
  529.     default:
  530.         link->speed = SWITCH_PORT_SPEED_UNKNOWN;
  531.         break;
  532.     }
  533. }
  534.  
  535. static struct sk_buff *
  536. ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
  537. {
  538.     struct ar8xxx_priv *priv = dev->phy_ptr;
  539.     unsigned char *buf;
  540.  
  541.     if (unlikely(!priv))
  542.         goto error;
  543.  
  544.     if (!priv->vlan)
  545.         goto send;
  546.  
  547.     if (unlikely(skb_headroom(skb) < 2)) {
  548.         if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
  549.             goto error;
  550.     }
  551.  
  552.     buf = skb_push(skb, 2);
  553.     buf[0] = 0x10;
  554.     buf[1] = 0x80;
  555.  
  556. send:
  557.     return skb;
  558.  
  559. error:
  560.     dev_kfree_skb_any(skb);
  561.     return NULL;
  562. }
  563.  
  564. static void
  565. ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
  566. {
  567.     struct ar8xxx_priv *priv;
  568.     unsigned char *buf;
  569.     int port, vlan;
  570.  
  571.     priv = dev->phy_ptr;
  572.     if (!priv)
  573.         return;
  574.  
  575.     /* don't strip the header if vlan mode is disabled */
  576.     if (!priv->vlan)
  577.         return;
  578.  
  579.     /* strip header, get vlan id */
  580.     buf = skb->data;
  581.     skb_pull(skb, 2);
  582.  
  583.     /* check for vlan header presence */
  584.     if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
  585.         return;
  586.  
  587.     port = buf[0] & 0xf;
  588.  
  589.     /* no need to fix up packets coming from a tagged source */
  590.     if (priv->chip_data.ar8216.vlan_tagged & BIT(port))
  591.         return;
  592.  
  593.     /* lookup port vid from local table, the switch passes an invalid vlan id */
  594.     vlan = priv->vlan_id[priv->pvid[port]];
  595.  
  596.     buf[14 + 2] &= 0xf0;
  597.     buf[14 + 2] |= vlan >> 8;
  598.     buf[15 + 2] = vlan & 0xff;
  599. }
  600.  
  601. static int
  602. ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
  603. {
  604.     int timeout = 20;
  605.     u32 t = 0;
  606.  
  607.     while (1) {
  608.         t = priv->read(priv, reg);
  609.         if ((t & mask) == val)
  610.             return 0;
  611.  
  612.         if (timeout-- <= 0)
  613.             break;
  614.  
  615.         udelay(10);
  616.     }
  617.  
  618.     pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
  619.            (unsigned int) reg, t, mask, val);
  620.     return -ETIMEDOUT;
  621. }
  622.  
  623. static void
  624. ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
  625. {
  626.     if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
  627.         return;
  628.     if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
  629.         val &= AR8216_VTUDATA_MEMBER;
  630.         val |= AR8216_VTUDATA_VALID;
  631.         priv->write(priv, AR8216_REG_VTU_DATA, val);
  632.     }
  633.     op |= AR8216_VTU_ACTIVE;
  634.     priv->write(priv, AR8216_REG_VTU, op);
  635. }
  636.  
  637. static void
  638. ar8216_vtu_flush(struct ar8xxx_priv *priv)
  639. {
  640.     ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
  641. }
  642.  
  643. static void
  644. ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vlan)
  645. {
  646.     u32 op;
  647.  
  648.     u32 vid = priv->vlan_id[vlan];
  649.     u32 port_mask = priv->vlan_table[vlan];
  650.    
  651.     op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
  652.    
  653.     ar8216_vtu_op(priv, op, port_mask);
  654. }
  655.  
  656. static int
  657. ar8216_atu_flush(struct ar8xxx_priv *priv)
  658. {
  659.     int ret;
  660.  
  661.     ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
  662.     if (!ret)
  663.         priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
  664.  
  665.     return ret;
  666. }
  667.  
  668. static u32
  669. ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
  670. {
  671.     return priv->read(priv, AR8216_REG_PORT_STATUS(port));
  672. }
  673.  
  674. static void
  675. ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
  676. {
  677.     u32 header;
  678.     u32 egress, ingress;
  679.     u32 pvid;
  680.  
  681.     if (priv->vlan) {
  682.         pvid = priv->vlan_id[priv->pvid[port]];
  683.         if (priv->chip_data.ar8216.vlan_tagged & BIT(port))
  684.             egress = AR8216_OUT_ADD_VLAN;
  685.         else
  686.             egress = AR8216_OUT_STRIP_VLAN;
  687.         ingress = AR8216_IN_SECURE;
  688.     } else {
  689.         pvid = port;
  690.         egress = AR8216_OUT_KEEP;
  691.         ingress = AR8216_IN_PORT_ONLY;
  692.     }
  693.    
  694.    
  695.  
  696.     if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
  697.         header = AR8216_PORT_CTRL_HEADER;
  698.     else
  699.         header = 0;
  700.  
  701.     ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
  702.            AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
  703.            AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
  704.            AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
  705.            AR8216_PORT_CTRL_LEARN | header |
  706.            (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
  707.            (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
  708.  
  709.     ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
  710.            AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
  711.            AR8216_PORT_VLAN_DEFAULT_ID,
  712.            (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
  713.            (ingress << AR8216_PORT_VLAN_MODE_S) |
  714.            (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
  715. }
  716.  
  717. static int
  718. ar8216_hw_init(struct ar8xxx_priv *priv)
  719. {
  720.     return 0;
  721. }
  722.  
  723. static void
  724. ar8216_init_globals(struct ar8xxx_priv *priv)
  725. {
  726.     /* standard atheros magic */
  727.     priv->write(priv, 0x38, 0xc000050e);
  728.  
  729.     ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
  730.            AR8216_GCTRL_MTU, 1518 + 8 + 2);
  731. }
  732.  
  733. static void
  734. ar8216_init_port(struct ar8xxx_priv *priv, int port)
  735. {
  736.     /* Enable port learning and tx */
  737.     priv->write(priv, AR8216_REG_PORT_CTRL(port),
  738.         AR8216_PORT_CTRL_LEARN |
  739.         (4 << AR8216_PORT_CTRL_STATE_S));
  740.  
  741.     priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
  742.  
  743.     if (port == AR8216_PORT_CPU) {
  744.         priv->write(priv, AR8216_REG_PORT_STATUS(port),
  745.             AR8216_PORT_STATUS_LINK_UP |
  746.             (ar8xxx_has_gige(priv) ?
  747.                                 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
  748.             AR8216_PORT_STATUS_TXMAC |
  749.             AR8216_PORT_STATUS_RXMAC |
  750.             (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
  751.             (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
  752.             AR8216_PORT_STATUS_DUPLEX);
  753.     } else {
  754.         priv->write(priv, AR8216_REG_PORT_STATUS(port),
  755.             AR8216_PORT_STATUS_LINK_AUTO);
  756.     }
  757. }
  758.  
  759. static const struct ar8xxx_chip ar8216_chip = {
  760.     .caps = AR8XXX_CAP_MIB_COUNTERS,
  761.  
  762.     .hw_init = ar8216_hw_init,
  763.     .init_globals = ar8216_init_globals,
  764.     .init_port = ar8216_init_port,
  765.     .setup_port = ar8216_setup_port,
  766.     .read_port_status = ar8216_read_port_status,
  767.     .atu_flush = ar8216_atu_flush,
  768.     .vtu_flush = ar8216_vtu_flush,
  769.     .vtu_load_vlan = ar8216_vtu_load_vlan,
  770.  
  771.     .num_mibs = ARRAY_SIZE(ar8216_mibs),
  772.     .mib_decs = ar8216_mibs,
  773. };
  774.  
  775. static void
  776. ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
  777. {
  778.     u32 egress, ingress;
  779.     u32 pvid;
  780.  
  781.     if (priv->vlan) {
  782.         pvid = priv->vlan_id[priv->pvid[port]];
  783.         if (priv->chip_data.ar8216.vlan_tagged & BIT(port))
  784.             egress = AR8216_OUT_ADD_VLAN;
  785.         else
  786.             egress = AR8216_OUT_STRIP_VLAN;
  787.         ingress = AR8216_IN_SECURE;
  788.     } else {
  789.         pvid = port;
  790.         egress = AR8216_OUT_KEEP;
  791.         ingress = AR8216_IN_PORT_ONLY;
  792.     }
  793.  
  794.     ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
  795.            AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
  796.            AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
  797.            AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
  798.            AR8216_PORT_CTRL_LEARN |
  799.            (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
  800.            (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
  801.  
  802.     ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
  803.            AR8236_PORT_VLAN_DEFAULT_ID,
  804.            (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
  805.  
  806.     ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
  807.            AR8236_PORT_VLAN2_VLAN_MODE |
  808.            AR8236_PORT_VLAN2_MEMBER,
  809.            (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
  810.            (members << AR8236_PORT_VLAN2_MEMBER_S));
  811. }
  812.  
  813. static int
  814. ar8236_hw_init(struct ar8xxx_priv *priv)
  815. {
  816.     int i;
  817.     struct mii_bus *bus;
  818.  
  819.     if (priv->initialized)
  820.         return 0;
  821.  
  822.     /* Initialize the PHYs */
  823.     bus = priv->mii_bus;
  824.     for (i = 0; i < 5; i++) {
  825.         mdiobus_write(bus, i, MII_ADVERTISE,
  826.                   ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
  827.                   ADVERTISE_PAUSE_ASYM);
  828.         mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
  829.     }
  830.     msleep(1000);
  831.  
  832.     priv->initialized = true;
  833.     return 0;
  834. }
  835.  
  836. static void
  837. ar8236_init_globals(struct ar8xxx_priv *priv)
  838. {
  839.     /* enable jumbo frames */
  840.     ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
  841.            AR8316_GCTRL_MTU, 9018 + 8 + 2);
  842.  
  843.     /* Enable MIB counters */
  844.     ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
  845.            (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
  846.            AR8236_MIB_EN);
  847. }
  848.  
  849. static const struct ar8xxx_chip ar8236_chip = {
  850.     .caps = AR8XXX_CAP_MIB_COUNTERS,
  851.     .hw_init = ar8236_hw_init,
  852.     .init_globals = ar8236_init_globals,
  853.     .init_port = ar8216_init_port,
  854.     .setup_port = ar8236_setup_port,
  855.     .read_port_status = ar8216_read_port_status,
  856.     .atu_flush = ar8216_atu_flush,
  857.     .vtu_flush = ar8216_vtu_flush,
  858.     .vtu_load_vlan = ar8216_vtu_load_vlan,
  859.  
  860.     .num_mibs = ARRAY_SIZE(ar8236_mibs),
  861.     .mib_decs = ar8236_mibs,
  862. };
  863.  
  864. static int
  865. ar8316_hw_init(struct ar8xxx_priv *priv)
  866. {
  867.     int i;
  868.     u32 val, newval;
  869.     struct mii_bus *bus;
  870.  
  871.     val = priv->read(priv, AR8316_REG_POSTRIP);
  872.  
  873.     if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
  874.         if (priv->port4_phy) {
  875.             /* value taken from Ubiquiti RouterStation Pro */
  876.             newval = 0x81461bea;
  877.             pr_info("ar8316: Using port 4 as PHY\n");
  878.         } else {
  879.             newval = 0x01261be2;
  880.             pr_info("ar8316: Using port 4 as switch port\n");
  881.         }
  882.     } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
  883.         /* value taken from AVM Fritz!Box 7390 sources */
  884.         newval = 0x010e5b71;
  885.     } else {
  886.         /* no known value for phy interface */
  887.         pr_err("ar8316: unsupported mii mode: %d.\n",
  888.                priv->phy->interface);
  889.         return -EINVAL;
  890.     }
  891.  
  892.     if (val == newval)
  893.         goto out;
  894.  
  895.     priv->write(priv, AR8316_REG_POSTRIP, newval);
  896.  
  897.     if (priv->port4_phy &&
  898.         priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
  899.         /* work around for phy4 rgmii mode */
  900.         ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
  901.         /* rx delay */
  902.         ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
  903.         /* tx delay */
  904.         ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
  905.         msleep(1000);
  906.     }
  907.  
  908.     /* Initialize the ports */
  909.     bus = priv->mii_bus;
  910.     for (i = 0; i < 5; i++) {
  911.         /* initialize the port itself */
  912.         mdiobus_write(bus, i, MII_ADVERTISE,
  913.             ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
  914.         mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
  915.         mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
  916.     }
  917.  
  918.     msleep(1000);
  919.  
  920. out:
  921.     priv->initialized = true;
  922.     return 0;
  923. }
  924.  
  925. static void
  926. ar8316_init_globals(struct ar8xxx_priv *priv)
  927. {
  928.     /* standard atheros magic */
  929.     priv->write(priv, 0x38, 0xc000050e);
  930.  
  931.     /* enable cpu port to receive multicast and broadcast frames */
  932.     priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
  933.  
  934.     /* enable jumbo frames */
  935.     ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
  936.            AR8316_GCTRL_MTU, 9018 + 8 + 2);
  937.  
  938.     /* Enable MIB counters */
  939.     ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
  940.            (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
  941.            AR8236_MIB_EN);
  942. }
  943.  
  944. static const struct ar8xxx_chip ar8316_chip = {
  945.     .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
  946.     .hw_init = ar8316_hw_init,
  947.     .init_globals = ar8316_init_globals,
  948.     .init_port = ar8216_init_port,
  949.     .setup_port = ar8216_setup_port,
  950.     .read_port_status = ar8216_read_port_status,
  951.     .atu_flush = ar8216_atu_flush,
  952.     .vtu_flush = ar8216_vtu_flush,
  953.     .vtu_load_vlan = ar8216_vtu_load_vlan,
  954.  
  955.     .num_mibs = ARRAY_SIZE(ar8236_mibs),
  956.     .mib_decs = ar8236_mibs,
  957. };
  958.  
  959. static u32
  960. ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
  961. {
  962.     u32 t;
  963.  
  964.     if (!cfg)
  965.         return 0;
  966.  
  967.     t = 0;
  968.     switch (cfg->mode) {
  969.     case AR8327_PAD_NC:
  970.         break;
  971.  
  972.     case AR8327_PAD_MAC2MAC_MII:
  973.         t = AR8327_PAD_MAC_MII_EN;
  974.         if (cfg->rxclk_sel)
  975.             t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
  976.         if (cfg->txclk_sel)
  977.             t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
  978.         break;
  979.  
  980.     case AR8327_PAD_MAC2MAC_GMII:
  981.         t = AR8327_PAD_MAC_GMII_EN;
  982.         if (cfg->rxclk_sel)
  983.             t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
  984.         if (cfg->txclk_sel)
  985.             t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
  986.         break;
  987.  
  988.     case AR8327_PAD_MAC_SGMII:
  989.         t = AR8327_PAD_SGMII_EN;
  990.  
  991.         /*
  992.          * WAR for the QUalcomm Atheros AP136 board.
  993.          * It seems that RGMII TX/RX delay settings needs to be
  994.          * applied for SGMII mode as well, The ethernet is not
  995.          * reliable without this.
  996.          */
  997.         t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
  998.         t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
  999.         if (cfg->rxclk_delay_en)
  1000.             t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
  1001.         if (cfg->txclk_delay_en)
  1002.             t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
  1003.  
  1004.         if (cfg->sgmii_delay_en)
  1005.             t |= AR8327_PAD_SGMII_DELAY_EN;
  1006.  
  1007.         break;
  1008.  
  1009.     case AR8327_PAD_MAC2PHY_MII:
  1010.         t = AR8327_PAD_PHY_MII_EN;
  1011.         if (cfg->rxclk_sel)
  1012.             t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
  1013.         if (cfg->txclk_sel)
  1014.             t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
  1015.         break;
  1016.  
  1017.     case AR8327_PAD_MAC2PHY_GMII:
  1018.         t = AR8327_PAD_PHY_GMII_EN;
  1019.         if (cfg->pipe_rxclk_sel)
  1020.             t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
  1021.         if (cfg->rxclk_sel)
  1022.             t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
  1023.         if (cfg->txclk_sel)
  1024.             t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
  1025.         break;
  1026.  
  1027.     case AR8327_PAD_MAC_RGMII:
  1028.         t = AR8327_PAD_RGMII_EN;
  1029.         t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
  1030.         t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
  1031.         if (cfg->rxclk_delay_en)
  1032.             t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
  1033.         if (cfg->txclk_delay_en)
  1034.             t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
  1035.         break;
  1036.  
  1037.     case AR8327_PAD_PHY_GMII:
  1038.         t = AR8327_PAD_PHYX_GMII_EN;
  1039.         break;
  1040.  
  1041.     case AR8327_PAD_PHY_RGMII:
  1042.         t = AR8327_PAD_PHYX_RGMII_EN;
  1043.         break;
  1044.  
  1045.     case AR8327_PAD_PHY_MII:
  1046.         t = AR8327_PAD_PHYX_MII_EN;
  1047.         break;
  1048.     }
  1049.  
  1050.     return t;
  1051. }
  1052.  
  1053. static void
  1054. ar8327_phy_fixup(struct ar8xxx_priv *priv, int phy)
  1055. {
  1056.     switch (priv->chip_rev) {
  1057.     case 1:
  1058.         /* For 100M waveform */
  1059.         ar8xxx_phy_dbg_write(priv, phy, 0, 0x02ea);
  1060.         /* Turn on Gigabit clock */
  1061.         ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
  1062.         break;
  1063.  
  1064.     case 2:
  1065.         ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x3c);
  1066.         ar8xxx_phy_mmd_write(priv, phy, 0x4007, 0x0);
  1067.         /* fallthrough */
  1068.     case 4:
  1069.         ar8xxx_phy_mmd_write(priv, phy, 0x3, 0x800d);
  1070.         ar8xxx_phy_mmd_write(priv, phy, 0x4003, 0x803f);
  1071.  
  1072.         ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x6860);
  1073.         ar8xxx_phy_dbg_write(priv, phy, 0x5, 0x2c46);
  1074.         ar8xxx_phy_dbg_write(priv, phy, 0x3c, 0x6000);
  1075.         break;
  1076.     }
  1077. }
  1078.  
  1079. static u32
  1080. ar8327_get_port_init_status(struct ar8327_port_cfg *cfg)
  1081. {
  1082.     u32 t;
  1083.  
  1084.     if (!cfg->force_link)
  1085.         return AR8216_PORT_STATUS_LINK_AUTO;
  1086.  
  1087.     t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
  1088.     t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
  1089.     t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
  1090.     t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
  1091.  
  1092.     switch (cfg->speed) {
  1093.     case AR8327_PORT_SPEED_10:
  1094.         t |= AR8216_PORT_SPEED_10M;
  1095.         break;
  1096.     case AR8327_PORT_SPEED_100:
  1097.         t |= AR8216_PORT_SPEED_100M;
  1098.         break;
  1099.     case AR8327_PORT_SPEED_1000:
  1100.         t |= AR8216_PORT_SPEED_1000M;
  1101.         break;
  1102.     }
  1103.  
  1104.     return t;
  1105. }
  1106.  
  1107. static int
  1108. ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
  1109.                struct ar8327_platform_data *pdata)
  1110. {
  1111.     struct ar8327_led_cfg *led_cfg;
  1112.     struct ar8327_data *data;
  1113.     u32 pos, new_pos;
  1114.     u32 t;
  1115.  
  1116.     if (!pdata)
  1117.         return -EINVAL;
  1118.  
  1119.     priv->get_port_link = pdata->get_port_link;
  1120.  
  1121.     data = &priv->chip_data.ar8327;
  1122.  
  1123.     data->port0_status = ar8327_get_port_init_status(&pdata->port0_cfg);
  1124.     data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
  1125.  
  1126.     t = ar8327_get_pad_cfg(pdata->pad0_cfg);
  1127.     if (chip_is_ar8337(priv))
  1128.         t |= AR8337_PAD_MAC06_EXCHANGE_EN;
  1129.  
  1130.     priv->write(priv, AR8327_REG_PAD0_MODE, t);
  1131.     t = ar8327_get_pad_cfg(pdata->pad5_cfg);
  1132.     priv->write(priv, AR8327_REG_PAD5_MODE, t);
  1133.     t = ar8327_get_pad_cfg(pdata->pad6_cfg);
  1134.     priv->write(priv, AR8327_REG_PAD6_MODE, t);
  1135.  
  1136.     pos = priv->read(priv, AR8327_REG_POWER_ON_STRIP);
  1137.     new_pos = pos;
  1138.  
  1139.     led_cfg = pdata->led_cfg;
  1140.     if (led_cfg) {
  1141.         if (led_cfg->open_drain)
  1142.             new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
  1143.         else
  1144.             new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
  1145.  
  1146.         priv->write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
  1147.         priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
  1148.         priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
  1149.         priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
  1150.  
  1151.         if (new_pos != pos)
  1152.             new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
  1153.     }
  1154.  
  1155.     if (pdata->sgmii_cfg) {
  1156.         t = pdata->sgmii_cfg->sgmii_ctrl;
  1157.         if (priv->chip_rev == 1)
  1158.             t |= AR8327_SGMII_CTRL_EN_PLL |
  1159.                  AR8327_SGMII_CTRL_EN_RX |
  1160.                  AR8327_SGMII_CTRL_EN_TX;
  1161.         else
  1162.             t &= ~(AR8327_SGMII_CTRL_EN_PLL |
  1163.                    AR8327_SGMII_CTRL_EN_RX |
  1164.                    AR8327_SGMII_CTRL_EN_TX);
  1165.  
  1166.         priv->write(priv, AR8327_REG_SGMII_CTRL, t);
  1167.  
  1168.         if (pdata->sgmii_cfg->serdes_aen)
  1169.             new_pos &= ~AR8327_POWER_ON_STRIP_SERDES_AEN;
  1170.         else
  1171.             new_pos |= AR8327_POWER_ON_STRIP_SERDES_AEN;
  1172.     }
  1173.  
  1174.     priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
  1175.  
  1176.     return 0;
  1177. }
  1178.  
  1179. #ifdef CONFIG_OF
  1180. static int
  1181. ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
  1182. {
  1183.     const __be32 *paddr;
  1184.     int len;
  1185.     int i;
  1186.  
  1187.     paddr = of_get_property(np, "qca,ar8327-initvals", &len);
  1188.     if (!paddr || len < (2 * sizeof(*paddr)))
  1189.         return -EINVAL;
  1190.  
  1191.     len /= sizeof(*paddr);
  1192.  
  1193.     for (i = 0; i < len - 1; i += 2) {
  1194.         u32 reg;
  1195.         u32 val;
  1196.  
  1197.         reg = be32_to_cpup(paddr + i);
  1198.         val = be32_to_cpup(paddr + i + 1);
  1199.  
  1200.         switch (reg) {
  1201.         case AR8327_REG_PORT_STATUS(0):
  1202.             priv->chip_data.ar8327.port0_status = val;
  1203.             break;
  1204.         case AR8327_REG_PORT_STATUS(6):
  1205.             priv->chip_data.ar8327.port6_status = val;
  1206.             break;
  1207.         default:
  1208.             priv->write(priv, reg, val);
  1209.             break;
  1210.         }
  1211.     }
  1212.  
  1213.     return 0;
  1214. }
  1215. #else
  1216. static inline int
  1217. ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
  1218. {
  1219.     return -EINVAL;
  1220. }
  1221. #endif
  1222.  
  1223. static int
  1224. ar8327_hw_init(struct ar8xxx_priv *priv)
  1225. {
  1226.     struct mii_bus *bus;
  1227.     int ret;
  1228.     int i;
  1229.  
  1230.     if (priv->phy->dev.of_node)
  1231.         ret = ar8327_hw_config_of(priv, priv->phy->dev.of_node);
  1232.     else
  1233.         ret = ar8327_hw_config_pdata(priv,
  1234.                          priv->phy->dev.platform_data);
  1235.  
  1236.     if (ret)
  1237.         return ret;
  1238.  
  1239.     bus = priv->mii_bus;
  1240.     for (i = 0; i < AR8327_NUM_PHYS; i++) {
  1241.         ar8327_phy_fixup(priv, i);
  1242.  
  1243.         /* start aneg on the PHY */
  1244.         mdiobus_write(bus, i, MII_ADVERTISE, ADVERTISE_ALL |
  1245.                              ADVERTISE_PAUSE_CAP |
  1246.                              ADVERTISE_PAUSE_ASYM);
  1247.         mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
  1248.         mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
  1249.     }
  1250.  
  1251.     msleep(1000);
  1252.  
  1253.     return 0;
  1254. }
  1255.  
  1256. static void
  1257. ar8327_init_globals(struct ar8xxx_priv *priv)
  1258. {
  1259.     u32 t;
  1260.  
  1261.     /* enable CPU port and disable mirror port */
  1262.     t = AR8327_FWD_CTRL0_CPU_PORT_EN |
  1263.         AR8327_FWD_CTRL0_MIRROR_PORT;
  1264.     priv->write(priv, AR8327_REG_FWD_CTRL0, t);
  1265.  
  1266.     /* forward multicast and broadcast frames to CPU */
  1267.     t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
  1268.         (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
  1269.         (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
  1270.     priv->write(priv, AR8327_REG_FWD_CTRL1, t);
  1271.  
  1272.     /* enable jumbo frames */
  1273.     ar8xxx_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
  1274.            AR8327_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2);
  1275.  
  1276.     /* Enable MIB counters */
  1277.     ar8xxx_reg_set(priv, AR8327_REG_MODULE_EN,
  1278.                AR8327_MODULE_EN_MIB);
  1279. }
  1280.  
  1281. static void
  1282. ar8327_init_port(struct ar8xxx_priv *priv, int port)
  1283. {
  1284.     u32 t;
  1285.  
  1286.     if (port == AR8216_PORT_CPU)
  1287.         t = priv->chip_data.ar8327.port0_status;
  1288.     else if (port == 6)
  1289.         t = priv->chip_data.ar8327.port6_status;
  1290.     else
  1291.         t = AR8216_PORT_STATUS_LINK_AUTO;
  1292.  
  1293.     priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
  1294.     priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
  1295.  
  1296.     t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
  1297.     t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
  1298.     priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
  1299.  
  1300.     t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
  1301.     priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
  1302.  
  1303.     t = AR8327_PORT_LOOKUP_LEARN;
  1304.     t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
  1305.     priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
  1306. }
  1307.  
  1308. static u32
  1309. ar8327_read_port_status(struct ar8xxx_priv *priv, int port)
  1310. {
  1311.     return priv->read(priv, AR8327_REG_PORT_STATUS(port));
  1312. }
  1313.  
  1314. static int
  1315. ar8327_atu_flush(struct ar8xxx_priv *priv)
  1316. {
  1317.     int ret;
  1318.  
  1319.     ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
  1320.                   AR8327_ATU_FUNC_BUSY, 0);
  1321.     if (!ret)
  1322.         priv->write(priv, AR8327_REG_ATU_FUNC,
  1323.                 AR8327_ATU_FUNC_OP_FLUSH);
  1324.  
  1325.     return ret;
  1326. }
  1327.  
  1328. static void
  1329. ar8327_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
  1330. {
  1331.     if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
  1332.                 AR8327_VTU_FUNC1_BUSY, 0))
  1333.         return;
  1334.  
  1335.     if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
  1336.         priv->write(priv, AR8327_REG_VTU_FUNC0, val);
  1337.  
  1338.     op |= AR8327_VTU_FUNC1_BUSY;
  1339.     priv->write(priv, AR8327_REG_VTU_FUNC1, op);
  1340. }
  1341.  
  1342. static void
  1343. ar8327_vtu_flush(struct ar8xxx_priv *priv)
  1344. {
  1345.     ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
  1346. }
  1347.  
  1348. static void
  1349. ar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vlan)
  1350. {
  1351.     u32 op, val;
  1352.     int i;
  1353.    
  1354.     u32 vid = priv->vlan_id[vlan];
  1355.     u32 port_mask = priv->vlan_table[vlan];
  1356.     u32 tagged = priv->chip_data.ar8327.vlan_tagged[vlan];
  1357.    
  1358.    
  1359.     op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
  1360.     val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
  1361.     for (i = 0; i < AR8327_NUM_PORTS; i++) {
  1362.         u32 mode;
  1363.  
  1364.         if ((port_mask & BIT(i)) == 0)
  1365.             mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
  1366.         else if (priv->vlan == 0)
  1367.             mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
  1368.         else if (tagged & BIT(i))
  1369.             mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
  1370.         else
  1371.             mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
  1372.  
  1373.         val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
  1374.     }
  1375.     ar8327_vtu_op(priv, op, val);
  1376. }
  1377.  
  1378. static void
  1379. ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
  1380. {
  1381.     u32 ingress, mode;
  1382.     u32 pvid;  
  1383.  
  1384.     u32 t;
  1385.    
  1386.     if (priv->vlan) {
  1387.         pvid = priv->vlan_id[priv->pvid[port]];
  1388.         mode = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
  1389.         ingress = AR8216_IN_SECURE;
  1390.     } else {
  1391.         pvid = port;
  1392.         mode = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
  1393.         ingress = AR8216_IN_PORT_ONLY;
  1394.     }
  1395.  
  1396.     t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
  1397.     t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
  1398.     priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
  1399.  
  1400.     t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
  1401.     t |= mode << AR8327_PORT_VLAN1_OUT_MODE_S;
  1402.     priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
  1403.  
  1404.     t = members;
  1405.     t |= AR8327_PORT_LOOKUP_LEARN;
  1406.     t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
  1407.     t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
  1408.     priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
  1409. }
  1410.  
  1411. static const struct ar8xxx_chip ar8327_chip = {
  1412.     .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
  1413.     .hw_init = ar8327_hw_init,
  1414.     .init_globals = ar8327_init_globals,
  1415.     .init_port = ar8327_init_port,
  1416.     .setup_port = ar8327_setup_port,
  1417.     .read_port_status = ar8327_read_port_status,
  1418.     .atu_flush = ar8327_atu_flush,
  1419.     .vtu_flush = ar8327_vtu_flush,
  1420.     .vtu_load_vlan = ar8327_vtu_load_vlan,
  1421.  
  1422.     .num_mibs = ARRAY_SIZE(ar8236_mibs),
  1423.     .mib_decs = ar8236_mibs,
  1424. };
  1425.  
  1426. static int
  1427. ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
  1428.            struct switch_val *val)
  1429. {
  1430.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1431.     priv->vlan = !!val->value.i;
  1432.     return 0;
  1433. }
  1434.  
  1435. static int
  1436. ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
  1437.            struct switch_val *val)
  1438. {
  1439.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1440.     val->value.i = priv->vlan;
  1441.     return 0;
  1442. }
  1443.  
  1444.  
  1445. static int
  1446. ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
  1447. {
  1448.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1449.  
  1450.     /* make sure no invalid PVIDs get set */
  1451.  
  1452.     if (vlan >= dev->vlans)
  1453.         return -EINVAL;
  1454.  
  1455.     priv->pvid[port] = vlan;
  1456.     return 0;
  1457. }
  1458.  
  1459. static int
  1460. ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
  1461. {
  1462.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1463.     *vlan = priv->pvid[port];
  1464.     return 0;
  1465. }
  1466.  
  1467. static int
  1468. ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
  1469.           struct switch_val *val)
  1470. {
  1471.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1472.     priv->vlan_id[val->port_vlan] = val->value.i;
  1473.     return 0;
  1474. }
  1475.  
  1476. static int
  1477. ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
  1478.           struct switch_val *val)
  1479. {
  1480.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1481.     val->value.i = priv->vlan_id[val->port_vlan];
  1482.     return 0;
  1483. }
  1484.  
  1485. static int
  1486. ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
  1487.             struct switch_port_link *link)
  1488. {
  1489.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1490.  
  1491.     ar8216_read_port_link(priv, port, link);
  1492.     return 0;
  1493. }
  1494.  
  1495. static int
  1496. ar8xxx_sw_get_ports(struct switch_val *val, int ports, u8 port_mask, u8 tagged)
  1497. {
  1498.     int i;
  1499.     val->len = 0;
  1500.     for (i = 0; i < ports; i++) {
  1501.         struct switch_port *p;
  1502.  
  1503.         if (!(port_mask & BIT(i)))
  1504.             continue;
  1505.  
  1506.         p = &val->value.ports[val->len++];
  1507.         p->id = i;
  1508.         if (tagged & BIT(i))
  1509.             p->flags = BIT(SWITCH_PORT_FLAG_TAGGED);
  1510.         else
  1511.             p->flags = 0;
  1512.     }
  1513.     return 0;
  1514. }
  1515.  
  1516. static int
  1517. ar8216_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
  1518. {
  1519.     int ports = dev->ports;
  1520.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1521.     u8 port_mask = priv->vlan_table[val->port_vlan];
  1522.     u8 tagged = priv->chip_data.ar8216.vlan_tagged;
  1523.    
  1524.     return ar8xxx_sw_get_ports(val, ports, port_mask, tagged);
  1525. }
  1526.  
  1527. static int
  1528. ar8327_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
  1529. {
  1530.     int ports = dev->ports;
  1531.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1532.     u8 port_mask = priv->vlan_table[val->port_vlan];
  1533.     u8 tagged = priv->chip_data.ar8327.vlan_tagged[val->port_vlan];
  1534.    
  1535.     return ar8xxx_sw_get_ports(val, ports, port_mask, tagged);
  1536. }
  1537.  
  1538. static int
  1539. ar8216_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
  1540. {
  1541.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1542.     u8 *vt = &priv->vlan_table[val->port_vlan];
  1543.     u8 *tagged = &priv->chip_data.ar8216.vlan_tagged;
  1544.    
  1545.     int i, j;
  1546.  
  1547.     *vt = 0;
  1548.     for (i = 0; i < val->len; i++) {
  1549.         struct switch_port *p = &val->value.ports[i];
  1550.  
  1551.         if (p->flags & BIT(SWITCH_PORT_FLAG_TAGGED)) {
  1552.            
  1553.             /* if port was untagged before then
  1554.              * remove him from other vlans */
  1555.             if(*tagged & BIT(p->id)){
  1556.                 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
  1557.                     if (j == val->port_vlan)
  1558.                         continue;
  1559.                
  1560.                     priv->vlan_table[j] &= ~(BIT(p->id));
  1561.                 }
  1562.             }
  1563.            
  1564.             *tagged |= BIT(p->id);
  1565.         } else {
  1566.             *tagged &= ~(BIT(p->id));
  1567.             priv->pvid[p->id] = val->port_vlan;
  1568.            
  1569.             /* make sure that an untagged port does not
  1570.             * appear in other vlans */
  1571.             for (j = 0; j < AR8X16_MAX_VLANS; j++) {
  1572.                 if (j == val->port_vlan)
  1573.                     continue;
  1574.                
  1575.                 priv->vlan_table[j] &= ~(BIT(p->id));
  1576.             }
  1577.         }
  1578.  
  1579.         *vt |= BIT(p->id);
  1580.     }
  1581.     return 0;
  1582. }
  1583.  
  1584. static int
  1585. ar8327_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
  1586. {
  1587.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1588.     u8 *vt = &priv->vlan_table[val->port_vlan];
  1589.     u8 *vlan_tagged = priv->chip_data.ar8327.vlan_tagged;
  1590.     u8 *tagged = &vlan_tagged[val->port_vlan];
  1591.    
  1592.     int i, j;
  1593.  
  1594.     *vt = 0;
  1595.     *tagged = 0;
  1596.     for (i = 0; i < val->len; i++) {
  1597.         struct switch_port *p = &val->value.ports[i];
  1598.  
  1599.         if (p->flags & BIT(SWITCH_PORT_FLAG_TAGGED)) {
  1600.             *tagged |= BIT(p->id);
  1601.         } else {
  1602.             priv->pvid[p->id] = val->port_vlan;
  1603.            
  1604.             /* make sure that an untagged port does not
  1605.             * appear in other vlans */
  1606.             for (j = 0; j < AR8X16_MAX_VLANS; j++) {
  1607.                 if (j == val->port_vlan)
  1608.                     continue;
  1609.                
  1610.                 // skip tagged
  1611.                 if(vlan_tagged[j] & BIT(SWITCH_PORT_FLAG_TAGGED))
  1612.                     continue;
  1613.                
  1614.                 // remove port
  1615.                 priv->vlan_table[j] &= ~(BIT(p->id));
  1616.             }
  1617.         }
  1618.  
  1619.         *vt |= BIT(p->id);
  1620.     }
  1621.     return 0;
  1622. }
  1623.  
  1624. static void
  1625. ar8327_set_mirror_regs(struct ar8xxx_priv *priv)
  1626. {
  1627.     int port;
  1628.  
  1629.     /* reset all mirror registers */
  1630.     ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
  1631.            AR8327_FWD_CTRL0_MIRROR_PORT,
  1632.            (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S));
  1633.     for (port = 0; port < AR8327_NUM_PORTS; port++) {
  1634.         ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(port),
  1635.                AR8327_PORT_LOOKUP_ING_MIRROR_EN,
  1636.                0);
  1637.  
  1638.         ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(port),
  1639.                AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
  1640.                0);
  1641.     }
  1642.  
  1643.     /* now enable mirroring if necessary */
  1644.     if (priv->source_port >= AR8327_NUM_PORTS ||
  1645.         priv->monitor_port >= AR8327_NUM_PORTS ||
  1646.         priv->source_port == priv->monitor_port) {
  1647.         return;
  1648.     }
  1649.  
  1650.     ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
  1651.            AR8327_FWD_CTRL0_MIRROR_PORT,
  1652.            (priv->monitor_port << AR8327_FWD_CTRL0_MIRROR_PORT_S));
  1653.  
  1654.     if (priv->mirror_rx)
  1655.         ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(priv->source_port),
  1656.                AR8327_PORT_LOOKUP_ING_MIRROR_EN,
  1657.                AR8327_PORT_LOOKUP_ING_MIRROR_EN);
  1658.  
  1659.     if (priv->mirror_tx)
  1660.         ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(priv->source_port),
  1661.                AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
  1662.                AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);
  1663. }
  1664.  
  1665. static void
  1666. ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
  1667. {
  1668.     int port;
  1669.  
  1670.     /* reset all mirror registers */
  1671.     ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
  1672.            AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
  1673.            (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
  1674.     for (port = 0; port < AR8216_NUM_PORTS; port++) {
  1675.         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
  1676.                AR8216_PORT_CTRL_MIRROR_RX,
  1677.                0);
  1678.  
  1679.         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
  1680.                AR8216_PORT_CTRL_MIRROR_TX,
  1681.                0);
  1682.     }
  1683.  
  1684.     /* now enable mirroring if necessary */
  1685.     if (priv->source_port >= AR8216_NUM_PORTS ||
  1686.         priv->monitor_port >= AR8216_NUM_PORTS ||
  1687.         priv->source_port == priv->monitor_port) {
  1688.         return;
  1689.     }
  1690.  
  1691.     ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
  1692.            AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
  1693.            (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
  1694.  
  1695.     if (priv->mirror_rx)
  1696.         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
  1697.                AR8216_PORT_CTRL_MIRROR_RX,
  1698.                AR8216_PORT_CTRL_MIRROR_RX);
  1699.  
  1700.     if (priv->mirror_tx)
  1701.         ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
  1702.                AR8216_PORT_CTRL_MIRROR_TX,
  1703.                AR8216_PORT_CTRL_MIRROR_TX);
  1704. }
  1705.  
  1706. static void
  1707. ar8xxx_set_mirror_regs(struct ar8xxx_priv *priv)
  1708. {
  1709.     if (chip_is_ar8327(priv) || chip_is_ar8337(priv)) {
  1710.         ar8327_set_mirror_regs(priv);
  1711.     } else {
  1712.         ar8216_set_mirror_regs(priv);
  1713.     }
  1714. }
  1715.  
  1716. static int
  1717. ar8xxx_sw_hw_apply(struct switch_dev *dev)
  1718. {
  1719.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1720.     u8 portmask[AR8X16_MAX_PORTS];
  1721.     int i, j;
  1722.  
  1723.     mutex_lock(&priv->reg_mutex);
  1724.     /* flush all vlan translation unit entries */
  1725.     priv->chip->vtu_flush(priv);
  1726.  
  1727.     memset(portmask, 0, sizeof(portmask));
  1728.     if (!priv->init) {
  1729.         /* calculate the port destination masks and load vlans
  1730.          * into the vlan translation unit */
  1731.         for (j = 0; j < AR8X16_MAX_VLANS; j++) {
  1732.             u8 vp = priv->vlan_table[j];
  1733.  
  1734.             if (!vp)
  1735.                 continue;
  1736.  
  1737.             for (i = 0; i < dev->ports; i++) {
  1738.                 u8 mask = BIT(i);
  1739.                 if (vp & mask)
  1740.                     portmask[i] |= vp & ~mask;
  1741.             }
  1742.             priv->chip->vtu_load_vlan(priv, j);
  1743.         }
  1744.     } else {
  1745.         /* vlan disabled:
  1746.          * isolate all ports, but connect them to the cpu port */
  1747.         for (i = 0; i < dev->ports; i++) {
  1748.             if (i == AR8216_PORT_CPU)
  1749.                 continue;
  1750.  
  1751.             portmask[i] = BIT(AR8216_PORT_CPU);
  1752.             portmask[AR8216_PORT_CPU] |= BIT(i);
  1753.         }
  1754.     }
  1755.  
  1756.     /* update the port destination mask registers and tag settings */
  1757.     for (i = 0; i < dev->ports; i++) {
  1758.         priv->chip->setup_port(priv, i, portmask[i]);
  1759.     }
  1760.  
  1761.     ar8xxx_set_mirror_regs(priv);
  1762.  
  1763.     mutex_unlock(&priv->reg_mutex);
  1764.     return 0;
  1765. }
  1766.  
  1767. static int
  1768. ar8xxx_sw_reset_switch(struct switch_dev *dev)
  1769. {
  1770.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1771.     int i;
  1772.  
  1773.     mutex_lock(&priv->reg_mutex);
  1774.     memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
  1775.         offsetof(struct ar8xxx_priv, vlan));
  1776.  
  1777.     for (i = 0; i < AR8X16_MAX_VLANS; i++)
  1778.         priv->vlan_id[i] = i;
  1779.  
  1780.     /* Configure all ports */
  1781.     for (i = 0; i < dev->ports; i++)
  1782.         priv->chip->init_port(priv, i);
  1783.  
  1784.     priv->mirror_rx = false;
  1785.     priv->mirror_tx = false;
  1786.     priv->source_port = 0;
  1787.     priv->monitor_port = 0;
  1788.  
  1789.     priv->chip->init_globals(priv);
  1790.  
  1791.     mutex_unlock(&priv->reg_mutex);
  1792.  
  1793.     return ar8xxx_sw_hw_apply(dev);
  1794. }
  1795.  
  1796. static int
  1797. ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
  1798.              const struct switch_attr *attr,
  1799.              struct switch_val *val)
  1800. {
  1801.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1802.     unsigned int len;
  1803.     int ret;
  1804.  
  1805.     if (!ar8xxx_has_mib_counters(priv))
  1806.         return -EOPNOTSUPP;
  1807.  
  1808.     mutex_lock(&priv->mib_lock);
  1809.  
  1810.     len = priv->dev.ports * priv->chip->num_mibs *
  1811.           sizeof(*priv->mib_stats);
  1812.     memset(priv->mib_stats, '\0', len);
  1813.     ret = ar8xxx_mib_flush(priv);
  1814.     if (ret)
  1815.         goto unlock;
  1816.  
  1817.     ret = 0;
  1818.  
  1819. unlock:
  1820.     mutex_unlock(&priv->mib_lock);
  1821.     return ret;
  1822. }
  1823.  
  1824. static int
  1825. ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
  1826.                    const struct switch_attr *attr,
  1827.                    struct switch_val *val)
  1828. {
  1829.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1830.  
  1831.     mutex_lock(&priv->reg_mutex);
  1832.     priv->mirror_rx = !!val->value.i;
  1833.     ar8xxx_set_mirror_regs(priv);
  1834.     mutex_unlock(&priv->reg_mutex);
  1835.  
  1836.     return 0;
  1837. }
  1838.  
  1839. static int
  1840. ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
  1841.                    const struct switch_attr *attr,
  1842.                    struct switch_val *val)
  1843. {
  1844.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1845.     val->value.i = priv->mirror_rx;
  1846.     return 0;
  1847. }
  1848.  
  1849. static int
  1850. ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
  1851.                    const struct switch_attr *attr,
  1852.                    struct switch_val *val)
  1853. {
  1854.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1855.  
  1856.     mutex_lock(&priv->reg_mutex);
  1857.     priv->mirror_tx = !!val->value.i;
  1858.     ar8xxx_set_mirror_regs(priv);
  1859.     mutex_unlock(&priv->reg_mutex);
  1860.  
  1861.     return 0;
  1862. }
  1863.  
  1864. static int
  1865. ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
  1866.                    const struct switch_attr *attr,
  1867.                    struct switch_val *val)
  1868. {
  1869.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1870.     val->value.i = priv->mirror_tx;
  1871.     return 0;
  1872. }
  1873.  
  1874. static int
  1875. ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
  1876.                   const struct switch_attr *attr,
  1877.                   struct switch_val *val)
  1878. {
  1879.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1880.  
  1881.     mutex_lock(&priv->reg_mutex);
  1882.     priv->monitor_port = val->value.i;
  1883.     ar8xxx_set_mirror_regs(priv);
  1884.     mutex_unlock(&priv->reg_mutex);
  1885.  
  1886.     return 0;
  1887. }
  1888.  
  1889. static int
  1890. ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
  1891.                   const struct switch_attr *attr,
  1892.                   struct switch_val *val)
  1893. {
  1894.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1895.     val->value.i = priv->monitor_port;
  1896.     return 0;
  1897. }
  1898.  
  1899. static int
  1900. ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
  1901.                  const struct switch_attr *attr,
  1902.                  struct switch_val *val)
  1903. {
  1904.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1905.  
  1906.     mutex_lock(&priv->reg_mutex);
  1907.     priv->source_port = val->value.i;
  1908.     ar8xxx_set_mirror_regs(priv);
  1909.     mutex_unlock(&priv->reg_mutex);
  1910.  
  1911.     return 0;
  1912. }
  1913.  
  1914. static int
  1915. ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
  1916.                  const struct switch_attr *attr,
  1917.                  struct switch_val *val)
  1918. {
  1919.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1920.     val->value.i = priv->source_port;
  1921.     return 0;
  1922. }
  1923.  
  1924. static int
  1925. ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
  1926.                  const struct switch_attr *attr,
  1927.                  struct switch_val *val)
  1928. {
  1929.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1930.     int port;
  1931.     int ret;
  1932.  
  1933.     if (!ar8xxx_has_mib_counters(priv))
  1934.         return -EOPNOTSUPP;
  1935.  
  1936.     port = val->port_vlan;
  1937.     if (port >= dev->ports)
  1938.         return -EINVAL;
  1939.  
  1940.     mutex_lock(&priv->mib_lock);
  1941.     ret = ar8xxx_mib_capture(priv);
  1942.     if (ret)
  1943.         goto unlock;
  1944.  
  1945.     ar8xxx_mib_fetch_port_stat(priv, port, true);
  1946.  
  1947.     ret = 0;
  1948.  
  1949. unlock:
  1950.     mutex_unlock(&priv->mib_lock);
  1951.     return ret;
  1952. }
  1953.  
  1954. static int
  1955. ar8xxx_sw_get_port_mib(struct switch_dev *dev,
  1956.                const struct switch_attr *attr,
  1957.                struct switch_val *val)
  1958. {
  1959.     struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1960.     const struct ar8xxx_chip *chip = priv->chip;
  1961.     u64 *mib_stats;
  1962.     int port;
  1963.     int ret;
  1964.     char *buf = priv->buf;
  1965.     int i, len = 0;
  1966.  
  1967.     if (!ar8xxx_has_mib_counters(priv))
  1968.         return -EOPNOTSUPP;
  1969.  
  1970.     port = val->port_vlan;
  1971.     if (port >= dev->ports)
  1972.         return -EINVAL;
  1973.  
  1974.     mutex_lock(&priv->mib_lock);
  1975.     ret = ar8xxx_mib_capture(priv);
  1976.     if (ret)
  1977.         goto unlock;
  1978.  
  1979.     ar8xxx_mib_fetch_port_stat(priv, port, false);
  1980.  
  1981.     len += snprintf(buf + len, sizeof(priv->buf) - len,
  1982.             "Port %d MIB counters\n",
  1983.             port);
  1984.  
  1985.     mib_stats = &priv->mib_stats[port * chip->num_mibs];
  1986.     for (i = 0; i < chip->num_mibs; i++)
  1987.         len += snprintf(buf + len, sizeof(priv->buf) - len,
  1988.                 "%-12s: %llu\n",
  1989.                 chip->mib_decs[i].name,
  1990.                 mib_stats[i]);
  1991.  
  1992.     val->value.s = buf;
  1993.     val->len = len;
  1994.  
  1995.     ret = 0;
  1996.  
  1997. unlock:
  1998.     mutex_unlock(&priv->mib_lock);
  1999.     return ret;
  2000. }
  2001.  
  2002. static struct switch_attr ar8xxx_sw_attr_globals[] = {
  2003.     {
  2004.         .type = SWITCH_TYPE_INT,
  2005.         .name = "enable_vlan",
  2006.         .description = "Enable VLAN mode",
  2007.         .set = ar8xxx_sw_set_vlan,
  2008.         .get = ar8xxx_sw_get_vlan,
  2009.         .max = 1
  2010.     },
  2011.     {
  2012.         .type = SWITCH_TYPE_NOVAL,
  2013.         .name = "reset_mibs",
  2014.         .description = "Reset all MIB counters",
  2015.         .set = ar8xxx_sw_set_reset_mibs,
  2016.     },
  2017.     {
  2018.         .type = SWITCH_TYPE_INT,
  2019.         .name = "enable_mirror_rx",
  2020.         .description = "Enable mirroring of RX packets",
  2021.         .set = ar8xxx_sw_set_mirror_rx_enable,
  2022.         .get = ar8xxx_sw_get_mirror_rx_enable,
  2023.         .max = 1
  2024.     },
  2025.     {
  2026.         .type = SWITCH_TYPE_INT,
  2027.         .name = "enable_mirror_tx",
  2028.         .description = "Enable mirroring of TX packets",
  2029.         .set = ar8xxx_sw_set_mirror_tx_enable,
  2030.         .get = ar8xxx_sw_get_mirror_tx_enable,
  2031.         .max = 1
  2032.     },
  2033.     {
  2034.         .type = SWITCH_TYPE_INT,
  2035.         .name = "mirror_monitor_port",
  2036.         .description = "Mirror monitor port",
  2037.         .set = ar8xxx_sw_set_mirror_monitor_port,
  2038.         .get = ar8xxx_sw_get_mirror_monitor_port,
  2039.         .max = AR8216_NUM_PORTS - 1
  2040.     },
  2041.     {
  2042.         .type = SWITCH_TYPE_INT,
  2043.         .name = "mirror_source_port",
  2044.         .description = "Mirror source port",
  2045.         .set = ar8xxx_sw_set_mirror_source_port,
  2046.         .get = ar8xxx_sw_get_mirror_source_port,
  2047.         .max = AR8216_NUM_PORTS - 1
  2048.     },
  2049. };
  2050.  
  2051. static struct switch_attr ar8327_sw_attr_globals[] = {
  2052.     {
  2053.         .type = SWITCH_TYPE_INT,
  2054.         .name = "enable_vlan",
  2055.         .description = "Enable VLAN mode",
  2056.         .set = ar8xxx_sw_set_vlan,
  2057.         .get = ar8xxx_sw_get_vlan,
  2058.         .max = 1
  2059.     },
  2060.     {
  2061.         .type = SWITCH_TYPE_NOVAL,
  2062.         .name = "reset_mibs",
  2063.         .description = "Reset all MIB counters",
  2064.         .set = ar8xxx_sw_set_reset_mibs,
  2065.     },
  2066.     {
  2067.         .type = SWITCH_TYPE_INT,
  2068.         .name = "enable_mirror_rx",
  2069.         .description = "Enable mirroring of RX packets",
  2070.         .set = ar8xxx_sw_set_mirror_rx_enable,
  2071.         .get = ar8xxx_sw_get_mirror_rx_enable,
  2072.         .max = 1
  2073.     },
  2074.     {
  2075.         .type = SWITCH_TYPE_INT,
  2076.         .name = "enable_mirror_tx",
  2077.         .description = "Enable mirroring of TX packets",
  2078.         .set = ar8xxx_sw_set_mirror_tx_enable,
  2079.         .get = ar8xxx_sw_get_mirror_tx_enable,
  2080.         .max = 1
  2081.     },
  2082.     {
  2083.         .type = SWITCH_TYPE_INT,
  2084.         .name = "mirror_monitor_port",
  2085.         .description = "Mirror monitor port",
  2086.         .set = ar8xxx_sw_set_mirror_monitor_port,
  2087.         .get = ar8xxx_sw_get_mirror_monitor_port,
  2088.         .max = AR8327_NUM_PORTS - 1
  2089.     },
  2090.     {
  2091.         .type = SWITCH_TYPE_INT,
  2092.         .name = "mirror_source_port",
  2093.         .description = "Mirror source port",
  2094.         .set = ar8xxx_sw_set_mirror_source_port,
  2095.         .get = ar8xxx_sw_get_mirror_source_port,
  2096.         .max = AR8327_NUM_PORTS - 1
  2097.     },
  2098. };
  2099.  
  2100. static struct switch_attr ar8xxx_sw_attr_port[] = {
  2101.     {
  2102.         .type = SWITCH_TYPE_NOVAL,
  2103.         .name = "reset_mib",
  2104.         .description = "Reset single port MIB counters",
  2105.         .set = ar8xxx_sw_set_port_reset_mib,
  2106.     },
  2107.     {
  2108.         .type = SWITCH_TYPE_STRING,
  2109.         .name = "mib",
  2110.         .description = "Get port's MIB counters",
  2111.         .set = NULL,
  2112.         .get = ar8xxx_sw_get_port_mib,
  2113.     },
  2114. };
  2115.  
  2116. static struct switch_attr ar8xxx_sw_attr_vlan[] = {
  2117.     {
  2118.         .type = SWITCH_TYPE_INT,
  2119.         .name = "vid",
  2120.         .description = "VLAN ID (0-4094)",
  2121.         .set = ar8xxx_sw_set_vid,
  2122.         .get = ar8xxx_sw_get_vid,
  2123.         .max = 4094,
  2124.     },
  2125. };
  2126.  
  2127. static const struct switch_dev_ops ar8xxx_sw_ops = {
  2128.     .attr_global = {
  2129.         .attr = ar8xxx_sw_attr_globals,
  2130.         .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
  2131.     },
  2132.     .attr_port = {
  2133.         .attr = ar8xxx_sw_attr_port,
  2134.         .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
  2135.     },
  2136.     .attr_vlan = {
  2137.         .attr = ar8xxx_sw_attr_vlan,
  2138.         .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
  2139.     },
  2140.     .get_port_pvid = ar8xxx_sw_get_pvid,
  2141.     .set_port_pvid = ar8xxx_sw_set_pvid,
  2142.     .get_vlan_ports = ar8216_sw_get_ports,
  2143.     .set_vlan_ports = ar8216_sw_set_ports,
  2144.     .apply_config = ar8xxx_sw_hw_apply,
  2145.     .reset_switch = ar8xxx_sw_reset_switch,
  2146.     .get_port_link = ar8xxx_sw_get_port_link,
  2147. };
  2148.  
  2149. static const struct switch_dev_ops ar8327_sw_ops = {
  2150.     .attr_global = {
  2151.         .attr = ar8327_sw_attr_globals,
  2152.         .n_attr = ARRAY_SIZE(ar8327_sw_attr_globals),
  2153.     },
  2154.     .attr_port = {
  2155.         .attr = ar8xxx_sw_attr_port,
  2156.         .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
  2157.     },
  2158.     .attr_vlan = {
  2159.         .attr = ar8xxx_sw_attr_vlan,
  2160.         .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
  2161.     },
  2162.     .get_port_pvid = ar8xxx_sw_get_pvid,
  2163.     .set_port_pvid = ar8xxx_sw_set_pvid,
  2164.     .get_vlan_ports = ar8327_sw_get_ports,
  2165.     .set_vlan_ports = ar8327_sw_set_ports,
  2166.     .apply_config = ar8xxx_sw_hw_apply,
  2167.     .reset_switch = ar8xxx_sw_reset_switch,
  2168.     .get_port_link = ar8xxx_sw_get_port_link,
  2169. };
  2170.  
  2171. static int
  2172. ar8xxx_id_chip(struct ar8xxx_priv *priv)
  2173. {
  2174.     u32 val;
  2175.     u16 id;
  2176.     int i;
  2177.  
  2178.     val = priv->read(priv, AR8216_REG_CTRL);
  2179.     if (val == ~0)
  2180.         return -ENODEV;
  2181.  
  2182.     id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
  2183.     for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
  2184.         u16 t;
  2185.  
  2186.         val = priv->read(priv, AR8216_REG_CTRL);
  2187.         if (val == ~0)
  2188.             return -ENODEV;
  2189.  
  2190.         t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
  2191.         if (t != id)
  2192.             return -ENODEV;
  2193.     }
  2194.  
  2195.     priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
  2196.     priv->chip_rev = (id & AR8216_CTRL_REVISION);
  2197.  
  2198.     switch (priv->chip_ver) {
  2199.     case AR8XXX_VER_AR8216:
  2200.         priv->chip = &ar8216_chip;
  2201.         break;
  2202.     case AR8XXX_VER_AR8236:
  2203.         priv->chip = &ar8236_chip;
  2204.         break;
  2205.     case AR8XXX_VER_AR8316:
  2206.         priv->chip = &ar8316_chip;
  2207.         break;
  2208.     case AR8XXX_VER_AR8327:
  2209.         priv->mii_lo_first = true;
  2210.         priv->chip = &ar8327_chip;
  2211.         break;
  2212.     case AR8XXX_VER_AR8337:
  2213.         priv->mii_lo_first = true;
  2214.         priv->chip = &ar8327_chip;
  2215.         break;
  2216.     default:
  2217.         pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
  2218.                priv->chip_ver, priv->chip_rev);
  2219.  
  2220.         return -ENODEV;
  2221.     }
  2222.  
  2223.     return 0;
  2224. }
  2225.  
  2226. static void
  2227. ar8xxx_mib_work_func(struct work_struct *work)
  2228. {
  2229.     struct ar8xxx_priv *priv;
  2230.     int err;
  2231.  
  2232.     priv = container_of(work, struct ar8xxx_priv, mib_work.work);
  2233.  
  2234.     mutex_lock(&priv->mib_lock);
  2235.  
  2236.     err = ar8xxx_mib_capture(priv);
  2237.     if (err)
  2238.         goto next_port;
  2239.  
  2240.     ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
  2241.  
  2242. next_port:
  2243.     priv->mib_next_port++;
  2244.     if (priv->mib_next_port >= priv->dev.ports)
  2245.         priv->mib_next_port = 0;
  2246.  
  2247.     mutex_unlock(&priv->mib_lock);
  2248.     schedule_delayed_work(&priv->mib_work,
  2249.                   msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
  2250. }
  2251.  
  2252. static int
  2253. ar8xxx_mib_init(struct ar8xxx_priv *priv)
  2254. {
  2255.     unsigned int len;
  2256.  
  2257.     if (!ar8xxx_has_mib_counters(priv))
  2258.         return 0;
  2259.  
  2260.     BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
  2261.  
  2262.     len = priv->dev.ports * priv->chip->num_mibs *
  2263.           sizeof(*priv->mib_stats);
  2264.     priv->mib_stats = kzalloc(len, GFP_KERNEL);
  2265.  
  2266.     if (!priv->mib_stats)
  2267.         return -ENOMEM;
  2268.  
  2269.     return 0;
  2270. }
  2271.  
  2272. static void
  2273. ar8xxx_mib_start(struct ar8xxx_priv *priv)
  2274. {
  2275.     if (!ar8xxx_has_mib_counters(priv))
  2276.         return;
  2277.  
  2278.     schedule_delayed_work(&priv->mib_work,
  2279.                   msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
  2280. }
  2281.  
  2282. static void
  2283. ar8xxx_mib_stop(struct ar8xxx_priv *priv)
  2284. {
  2285.     if (!ar8xxx_has_mib_counters(priv))
  2286.         return;
  2287.  
  2288.     cancel_delayed_work(&priv->mib_work);
  2289. }
  2290.  
  2291. static struct ar8xxx_priv *
  2292. ar8xxx_create(void)
  2293. {
  2294.     struct ar8xxx_priv *priv;
  2295.  
  2296.     priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
  2297.     if (priv == NULL)
  2298.         return NULL;
  2299.  
  2300.     mutex_init(&priv->reg_mutex);
  2301.     mutex_init(&priv->mib_lock);
  2302.     INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
  2303.  
  2304.     return priv;
  2305. }
  2306.  
  2307. static void
  2308. ar8xxx_free(struct ar8xxx_priv *priv)
  2309. {
  2310.     kfree(priv->mib_stats);
  2311.     kfree(priv);
  2312. }
  2313.  
  2314. static struct ar8xxx_priv *
  2315. ar8xxx_create_mii(struct mii_bus *bus)
  2316. {
  2317.     struct ar8xxx_priv *priv;
  2318.  
  2319.     priv = ar8xxx_create();
  2320.     if (priv) {
  2321.         priv->mii_bus = bus;
  2322.         priv->read = ar8xxx_mii_read;
  2323.         priv->write = ar8xxx_mii_write;
  2324.     }
  2325.  
  2326.     return priv;
  2327. }
  2328.  
  2329. static int
  2330. ar8xxx_probe_switch(struct ar8xxx_priv *priv)
  2331. {
  2332.     struct switch_dev *swdev;
  2333.     int ret;
  2334.  
  2335.     ret = ar8xxx_id_chip(priv);
  2336.     if (ret)
  2337.         return ret;
  2338.  
  2339.     swdev = &priv->dev;
  2340.     swdev->cpu_port = AR8216_PORT_CPU;
  2341.     swdev->ops = &ar8xxx_sw_ops;
  2342.  
  2343.     if (chip_is_ar8316(priv)) {
  2344.         swdev->name = "Atheros AR8316";
  2345.         swdev->vlans = AR8X16_MAX_VLANS;
  2346.         swdev->ports = AR8216_NUM_PORTS;
  2347.     } else if (chip_is_ar8236(priv)) {
  2348.         swdev->name = "Atheros AR8236";
  2349.         swdev->vlans = AR8216_NUM_VLANS;
  2350.         swdev->ports = AR8216_NUM_PORTS;
  2351.     } else if (chip_is_ar8327(priv)) {
  2352.         swdev->name = "Atheros AR8327";
  2353.         swdev->vlans = AR8X16_MAX_VLANS;
  2354.         swdev->ports = AR8327_NUM_PORTS;
  2355.         swdev->ops = &ar8327_sw_ops;
  2356.     } else if (chip_is_ar8337(priv)) {
  2357.         swdev->name = "Atheros AR8337";
  2358.         swdev->vlans = AR8X16_MAX_VLANS;
  2359.         swdev->ports = AR8327_NUM_PORTS;
  2360.         swdev->ops = &ar8327_sw_ops;
  2361.     } else {
  2362.         swdev->name = "Atheros AR8216";
  2363.         swdev->vlans = AR8216_NUM_VLANS;
  2364.         swdev->ports = AR8216_NUM_PORTS;
  2365.     }
  2366.  
  2367.     ret = ar8xxx_mib_init(priv);
  2368.     if (ret)
  2369.         return ret;
  2370.  
  2371.     return 0;
  2372. }
  2373.  
  2374. static int
  2375. ar8xxx_start(struct ar8xxx_priv *priv)
  2376. {
  2377.     int ret;
  2378.  
  2379.     priv->init = true;
  2380.  
  2381.     ret = priv->chip->hw_init(priv);
  2382.     if (ret)
  2383.         return ret;
  2384.  
  2385.     ret = ar8xxx_sw_reset_switch(&priv->dev);
  2386.     if (ret)
  2387.         return ret;
  2388.  
  2389.     priv->init = false;
  2390.  
  2391.     ar8xxx_mib_start(priv);
  2392.  
  2393.     return 0;
  2394. }
  2395.  
  2396. static int
  2397. ar8xxx_phy_config_init(struct phy_device *phydev)
  2398. {
  2399.     struct ar8xxx_priv *priv = phydev->priv;
  2400.     struct net_device *dev = phydev->attached_dev;
  2401.     int ret;
  2402.  
  2403.     if (WARN_ON(!priv))
  2404.         return -ENODEV;
  2405.  
  2406.     if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
  2407.         return 0;
  2408.  
  2409.     priv->phy = phydev;
  2410.  
  2411.     if (phydev->addr != 0) {
  2412.         if (chip_is_ar8316(priv)) {
  2413.             /* switch device has been initialized, reinit */
  2414.             priv->dev.ports = (AR8216_NUM_PORTS - 1);
  2415.             priv->initialized = false;
  2416.             priv->port4_phy = true;
  2417.             ar8316_hw_init(priv);
  2418.             return 0;
  2419.         }
  2420.  
  2421.         return 0;
  2422.     }
  2423.  
  2424.     ret = ar8xxx_start(priv);
  2425.     if (ret)
  2426.         return ret;
  2427.  
  2428.     /* VID fixup only needed on ar8216 */
  2429.     if (chip_is_ar8216(priv)) {
  2430.         dev->phy_ptr = priv;
  2431.         dev->priv_flags |= IFF_NO_IP_ALIGN;
  2432.         dev->eth_mangle_rx = ar8216_mangle_rx;
  2433.         dev->eth_mangle_tx = ar8216_mangle_tx;
  2434.     }
  2435.  
  2436.     return 0;
  2437. }
  2438.  
  2439. static int
  2440. ar8xxx_phy_read_status(struct phy_device *phydev)
  2441. {
  2442.     struct ar8xxx_priv *priv = phydev->priv;
  2443.     struct switch_port_link link;
  2444.     int ret;
  2445.  
  2446.     if (phydev->addr != 0)
  2447.         return genphy_read_status(phydev);
  2448.  
  2449.     ar8216_read_port_link(priv, phydev->addr, &link);
  2450.     phydev->link = !!link.link;
  2451.     if (!phydev->link)
  2452.         return 0;
  2453.  
  2454.     switch (link.speed) {
  2455.     case SWITCH_PORT_SPEED_10:
  2456.         phydev->speed = SPEED_10;
  2457.         break;
  2458.     case SWITCH_PORT_SPEED_100:
  2459.         phydev->speed = SPEED_100;
  2460.         break;
  2461.     case SWITCH_PORT_SPEED_1000:
  2462.         phydev->speed = SPEED_1000;
  2463.         break;
  2464.     default:
  2465.         phydev->speed = 0;
  2466.     }
  2467.     phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
  2468.  
  2469.     /* flush the address translation unit */
  2470.     mutex_lock(&priv->reg_mutex);
  2471.     ret = priv->chip->atu_flush(priv);
  2472.     mutex_unlock(&priv->reg_mutex);
  2473.  
  2474.     phydev->state = PHY_RUNNING;
  2475.     netif_carrier_on(phydev->attached_dev);
  2476.     phydev->adjust_link(phydev->attached_dev);
  2477.  
  2478.     return ret;
  2479. }
  2480.  
  2481. static int
  2482. ar8xxx_phy_config_aneg(struct phy_device *phydev)
  2483. {
  2484.     if (phydev->addr == 0)
  2485.         return 0;
  2486.  
  2487.     return genphy_config_aneg(phydev);
  2488. }
  2489.  
  2490. static const u32 ar8xxx_phy_ids[] = {
  2491.     0x004dd033,
  2492.     0x004dd034, /* AR8327 */
  2493.     0x004dd036, /* AR8337 */
  2494.     0x004dd041,
  2495.     0x004dd042,
  2496. };
  2497.  
  2498. static bool
  2499. ar8xxx_phy_match(u32 phy_id)
  2500. {
  2501.     int i;
  2502.  
  2503.     for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
  2504.         if (phy_id == ar8xxx_phy_ids[i])
  2505.             return true;
  2506.  
  2507.     return false;
  2508. }
  2509.  
  2510. static bool
  2511. ar8xxx_is_possible(struct mii_bus *bus)
  2512. {
  2513.     unsigned i;
  2514.  
  2515.     for (i = 0; i < 4; i++) {
  2516.         u32 phy_id;
  2517.  
  2518.         phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
  2519.         phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
  2520.         if (!ar8xxx_phy_match(phy_id)) {
  2521.             pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
  2522.                  dev_name(&bus->dev), i, phy_id);
  2523.             return false;
  2524.         }
  2525.     }
  2526.  
  2527.     return true;
  2528. }
  2529.  
  2530. static int
  2531. ar8xxx_phy_probe(struct phy_device *phydev)
  2532. {
  2533.     struct ar8xxx_priv *priv;
  2534.     struct switch_dev *swdev;
  2535.     int ret;
  2536.  
  2537.     /* skip PHYs at unused adresses */
  2538.     if (phydev->addr != 0 && phydev->addr != 4)
  2539.         return -ENODEV;
  2540.  
  2541.     if (!ar8xxx_is_possible(phydev->bus))
  2542.         return -ENODEV;
  2543.  
  2544.     mutex_lock(&ar8xxx_dev_list_lock);
  2545.     list_for_each_entry(priv, &ar8xxx_dev_list, list)
  2546.         if (priv->mii_bus == phydev->bus)
  2547.             goto found;
  2548.  
  2549.     priv = ar8xxx_create_mii(phydev->bus);
  2550.     if (priv == NULL) {
  2551.         ret = -ENOMEM;
  2552.         goto unlock;
  2553.     }
  2554.  
  2555.     ret = ar8xxx_probe_switch(priv);
  2556.     if (ret)
  2557.         goto free_priv;
  2558.  
  2559.     swdev = &priv->dev;
  2560.     swdev->alias = dev_name(&priv->mii_bus->dev);
  2561.     ret = register_switch(swdev, NULL);
  2562.     if (ret)
  2563.         goto free_priv;
  2564.  
  2565.     pr_info("%s: %s rev. %u switch registered on %s\n",
  2566.         swdev->devname, swdev->name, priv->chip_rev,
  2567.         dev_name(&priv->mii_bus->dev));
  2568.  
  2569. found:
  2570.     priv->use_count++;
  2571.  
  2572.     if (phydev->addr == 0) {
  2573.         if (ar8xxx_has_gige(priv)) {
  2574.             phydev->supported = SUPPORTED_1000baseT_Full;
  2575.             phydev->advertising = ADVERTISED_1000baseT_Full;
  2576.         } else {
  2577.             phydev->supported = SUPPORTED_100baseT_Full;
  2578.             phydev->advertising = ADVERTISED_100baseT_Full;
  2579.         }
  2580.  
  2581.         if (chip_is_ar8327(priv) || chip_is_ar8337(priv)) {
  2582.             priv->phy = phydev;
  2583.  
  2584.             ret = ar8xxx_start(priv);
  2585.             if (ret)
  2586.                 goto err_unregister_switch;
  2587.         }
  2588.     } else {
  2589.         if (ar8xxx_has_gige(priv)) {
  2590.             phydev->supported |= SUPPORTED_1000baseT_Full;
  2591.             phydev->advertising |= ADVERTISED_1000baseT_Full;
  2592.         }
  2593.     }
  2594.  
  2595.     phydev->priv = priv;
  2596.  
  2597.     list_add(&priv->list, &ar8xxx_dev_list);
  2598.  
  2599.     mutex_unlock(&ar8xxx_dev_list_lock);
  2600.  
  2601.     return 0;
  2602.  
  2603. err_unregister_switch:
  2604.     if (--priv->use_count)
  2605.         goto unlock;
  2606.  
  2607.     unregister_switch(&priv->dev);
  2608.  
  2609. free_priv:
  2610.     ar8xxx_free(priv);
  2611. unlock:
  2612.     mutex_unlock(&ar8xxx_dev_list_lock);
  2613.     return ret;
  2614. }
  2615.  
  2616. static void
  2617. ar8xxx_phy_detach(struct phy_device *phydev)
  2618. {
  2619.     struct net_device *dev = phydev->attached_dev;
  2620.  
  2621.     if (!dev)
  2622.         return;
  2623.  
  2624.     dev->phy_ptr = NULL;
  2625.     dev->priv_flags &= ~IFF_NO_IP_ALIGN;
  2626.     dev->eth_mangle_rx = NULL;
  2627.     dev->eth_mangle_tx = NULL;
  2628. }
  2629.  
  2630. static void
  2631. ar8xxx_phy_remove(struct phy_device *phydev)
  2632. {
  2633.     struct ar8xxx_priv *priv = phydev->priv;
  2634.  
  2635.     if (WARN_ON(!priv))
  2636.         return;
  2637.  
  2638.     phydev->priv = NULL;
  2639.     if (--priv->use_count > 0)
  2640.         return;
  2641.  
  2642.     mutex_lock(&ar8xxx_dev_list_lock);
  2643.     list_del(&priv->list);
  2644.     mutex_unlock(&ar8xxx_dev_list_lock);
  2645.  
  2646.     unregister_switch(&priv->dev);
  2647.     ar8xxx_mib_stop(priv);
  2648.     ar8xxx_free(priv);
  2649. }
  2650.  
  2651. static struct phy_driver ar8xxx_phy_driver = {
  2652.     .phy_id     = 0x004d0000,
  2653.     .name       = "Atheros AR8216/AR8236/AR8316",
  2654.     .phy_id_mask    = 0xffff0000,
  2655.     .features   = PHY_BASIC_FEATURES,
  2656.     .probe      = ar8xxx_phy_probe,
  2657.     .remove     = ar8xxx_phy_remove,
  2658.     .detach     = ar8xxx_phy_detach,
  2659.     .config_init    = ar8xxx_phy_config_init,
  2660.     .config_aneg    = ar8xxx_phy_config_aneg,
  2661.     .read_status    = ar8xxx_phy_read_status,
  2662.     .driver     = { .owner = THIS_MODULE },
  2663. };
  2664.  
  2665. int __init
  2666. ar8xxx_init(void)
  2667. {
  2668.     return phy_driver_register(&ar8xxx_phy_driver);
  2669. }
  2670.  
  2671. void __exit
  2672. ar8xxx_exit(void)
  2673. {
  2674.     phy_driver_unregister(&ar8xxx_phy_driver);
  2675. }
  2676.  
  2677. module_init(ar8xxx_init);
  2678. module_exit(ar8xxx_exit);
  2679. MODULE_LICENSE("GPL");
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