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- --------------------------------------------------------------------------------
- Release 14.7 Trace (lin64)
- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
- /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/trce -intstyle ise -v 3 -s 2 -n
- 3 -fastpaths -xml orpsoc_top.twx orpsoc_top.ncd -o orpsoc_top.twr
- orpsoc_top.pcf
- Design file: orpsoc_top.ncd
- Physical constraint file: orpsoc_top.pcf
- Device,package,speed: xc7a100t,csg324,C,-2 (PRODUCTION 1.10 2013-10-13)
- Report level: verbose report
- Environment Variable Effect
- -------------------- ------
- NONE No environment variables were set
- --------------------------------------------------------------------------------
- INFO:Timing:2698 - No timing constraints found, doing default enumeration.
- INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
- INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
- option. All paths that are not constrained will be reported in the
- unconstrained paths section(s) of the report.
- INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
- a 50 Ohm transmission line loading model. For the details of this model,
- and for more information on accounting for different loading conditions,
- please see the device datasheet.
- Data Sheet report:
- -----------------
- All values displayed in nanoseconds (ns)
- Setup/Hold to clock sys_clk_pad_i
- -------------------+------------+------------+------------+------------+------------------+--------+
- |Max Setup to| Process |Max Hold to | Process | | Clock |
- Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase |
- -------------------+------------+------------+------------+------------+------------------+--------+
- cellram_data_io<0> | 5.135(R)| SLOW | -1.939(R)| FAST |wb_clk | 0.000|
- cellram_data_io<1> | 5.847(R)| SLOW | -2.117(R)| FAST |wb_clk | 0.000|
- cellram_data_io<2> | 5.788(R)| SLOW | -2.109(R)| FAST |wb_clk | 0.000|
- cellram_data_io<3> | 5.419(R)| SLOW | -1.729(R)| FAST |wb_clk | 0.000|
- cellram_data_io<4> | 5.761(R)| SLOW | -1.982(R)| FAST |wb_clk | 0.000|
- cellram_data_io<5> | 5.464(R)| SLOW | -1.746(R)| FAST |wb_clk | 0.000|
- cellram_data_io<6> | 5.055(R)| SLOW | -1.959(R)| FAST |wb_clk | 0.000|
- cellram_data_io<7> | 4.701(R)| SLOW | -1.880(R)| FAST |wb_clk | 0.000|
- cellram_data_io<8> | 5.910(R)| SLOW | -2.153(R)| FAST |wb_clk | 0.000|
- cellram_data_io<9> | 5.286(R)| SLOW | -2.007(R)| FAST |wb_clk | 0.000|
- cellram_data_io<10>| 5.822(R)| SLOW | -2.158(R)| FAST |wb_clk | 0.000|
- cellram_data_io<11>| 5.700(R)| SLOW | -1.973(R)| FAST |wb_clk | 0.000|
- cellram_data_io<12>| 5.346(R)| SLOW | -1.886(R)| FAST |wb_clk | 0.000|
- cellram_data_io<13>| 5.345(R)| SLOW | -1.928(R)| FAST |wb_clk | 0.000|
- cellram_data_io<14>| 5.309(R)| SLOW | -1.834(R)| FAST |wb_clk | 0.000|
- cellram_data_io<15>| 5.754(R)| SLOW | -2.019(R)| FAST |wb_clk | 0.000|
- gpio0_io<0> | 3.931(R)| SLOW | -1.741(R)| FAST |wb_clk | 0.000|
- gpio0_io<1> | 3.943(R)| SLOW | -1.761(R)| FAST |wb_clk | 0.000|
- gpio0_io<2> | 4.033(R)| SLOW | -1.772(R)| FAST |wb_clk | 0.000|
- gpio0_io<3> | 3.682(R)| SLOW | -1.655(R)| FAST |wb_clk | 0.000|
- gpio0_io<4> | 4.085(R)| SLOW | -1.822(R)| FAST |wb_clk | 0.000|
- gpio0_io<5> | 3.958(R)| SLOW | -1.755(R)| FAST |wb_clk | 0.000|
- gpio0_io<6> | 4.055(R)| SLOW | -1.794(R)| FAST |wb_clk | 0.000|
- gpio0_io<7> | 4.183(R)| SLOW | -1.822(R)| FAST |wb_clk | 0.000|
- rst_n_pad_i | 5.632(R)| SLOW | -2.396(R)| FAST |wb_clk | 0.000|
- uart0_srx_pad_i | 4.014(R)| SLOW | -1.750(R)| FAST |wb_clk | 0.000|
- -------------------+------------+------------+------------+------------+------------------+--------+
- Clock sys_clk_pad_i to Pad
- -------------------+-----------------+------------+-----------------+------------+------------------+--------+
- |Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock |
- Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase |
- -------------------+-----------------+------------+-----------------+------------+------------------+--------+
- cellram_adr_o<0> | 5.507(R)| SLOW | 1.626(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<1> | 5.864(R)| SLOW | 1.829(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<2> | 5.643(R)| SLOW | 1.696(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<3> | 6.286(R)| SLOW | 2.011(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<4> | 6.038(R)| SLOW | 1.886(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<5> | 5.771(R)| SLOW | 1.765(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<6> | 5.857(R)| SLOW | 1.845(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<7> | 5.670(R)| SLOW | 1.741(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<8> | 5.497(R)| SLOW | 1.636(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<9> | 6.004(R)| SLOW | 1.989(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<10> | 6.301(R)| SLOW | 2.143(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<11> | 5.867(R)| SLOW | 1.901(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<12> | 5.508(R)| SLOW | 1.721(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<13> | 5.464(R)| SLOW | 1.650(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<14> | 6.010(R)| SLOW | 1.963(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<15> | 6.000(R)| SLOW | 1.942(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<16> | 5.207(R)| SLOW | 1.575(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<17> | 5.432(R)| SLOW | 1.697(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<18> | 5.415(R)| SLOW | 1.612(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<19> | 5.254(R)| SLOW | 1.539(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<20> | 5.543(R)| SLOW | 1.674(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<21> | 5.873(R)| SLOW | 1.878(R)| FAST |wb_clk | 0.000|
- cellram_adr_o<22> | 5.564(R)| SLOW | 1.721(R)| FAST |wb_clk | 0.000|
- cellram_adv_n_o | 5.321(R)| SLOW | 1.581(R)| FAST |wb_clk | 0.000|
- cellram_ce_n_o | 5.580(R)| SLOW | 1.776(R)| FAST |wb_clk | 0.000|
- cellram_cre_o | 5.808(R)| SLOW | 1.826(R)| FAST |wb_clk | 0.000|
- cellram_data_io<0> | 10.331(R)| SLOW | 1.813(R)| FAST |wb_clk | 0.000|
- cellram_data_io<1> | 10.268(R)| SLOW | 1.703(R)| FAST |wb_clk | 0.000|
- cellram_data_io<2> | 10.403(R)| SLOW | 1.747(R)| FAST |wb_clk | 0.000|
- cellram_data_io<3> | 10.207(R)| SLOW | 1.706(R)| FAST |wb_clk | 0.000|
- cellram_data_io<4> | 10.020(R)| SLOW | 1.920(R)| FAST |wb_clk | 0.000|
- cellram_data_io<5> | 9.456(R)| SLOW | 1.582(R)| FAST |wb_clk | 0.000|
- cellram_data_io<6> | 9.837(R)| SLOW | 1.636(R)| FAST |wb_clk | 0.000|
- cellram_data_io<7> | 9.956(R)| SLOW | 1.894(R)| FAST |wb_clk | 0.000|
- cellram_data_io<8> | 11.138(R)| SLOW | 1.907(R)| FAST |wb_clk | 0.000|
- cellram_data_io<9> | 11.283(R)| SLOW | 1.876(R)| FAST |wb_clk | 0.000|
- cellram_data_io<10>| 11.537(R)| SLOW | 1.725(R)| FAST |wb_clk | 0.000|
- cellram_data_io<11>| 10.427(R)| SLOW | 1.832(R)| FAST |wb_clk | 0.000|
- cellram_data_io<12>| 9.320(R)| SLOW | 1.732(R)| FAST |wb_clk | 0.000|
- cellram_data_io<13>| 9.461(R)| SLOW | 1.756(R)| FAST |wb_clk | 0.000|
- cellram_data_io<14>| 9.577(R)| SLOW | 1.718(R)| FAST |wb_clk | 0.000|
- cellram_data_io<15>| 9.334(R)| SLOW | 1.679(R)| FAST |wb_clk | 0.000|
- cellram_lb_n_o | 5.883(R)| SLOW | 1.835(R)| FAST |wb_clk | 0.000|
- cellram_oe_n_o | 6.276(R)| SLOW | 2.110(R)| FAST |wb_clk | 0.000|
- cellram_ub_n_o | 5.641(R)| SLOW | 1.703(R)| FAST |wb_clk | 0.000|
- cellram_we_n_o | 5.553(R)| SLOW | 1.751(R)| FAST |wb_clk | 0.000|
- gpio0_io<0> | 5.665(R)| SLOW | 1.685(R)| FAST |wb_clk | 0.000|
- gpio0_io<1> | 5.286(R)| SLOW | 1.525(R)| FAST |wb_clk | 0.000|
- gpio0_io<2> | 5.721(R)| SLOW | 1.706(R)| FAST |wb_clk | 0.000|
- gpio0_io<3> | 5.869(R)| SLOW | 1.672(R)| FAST |wb_clk | 0.000|
- gpio0_io<4> | 5.688(R)| SLOW | 1.711(R)| FAST |wb_clk | 0.000|
- gpio0_io<5> | 5.555(R)| SLOW | 1.660(R)| FAST |wb_clk | 0.000|
- gpio0_io<6> | 5.710(R)| SLOW | 1.683(R)| FAST |wb_clk | 0.000|
- gpio0_io<7> | 5.843(R)| SLOW | 1.763(R)| FAST |wb_clk | 0.000|
- uart0_stx_pad_o | 8.570(R)| SLOW | 3.117(R)| FAST |wb_clk | 0.000|
- -------------------+-----------------+------------+-----------------+------------+------------------+--------+
- Clock to Setup on destination clock sys_clk_pad_i
- ---------------+---------+---------+---------+---------+
- | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
- Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
- ---------------+---------+---------+---------+---------+
- sys_clk_pad_i | 12.155| | | |
- ---------------+---------+---------+---------+---------+
- Analysis completed Mon Apr 14 18:19:38 2014
- --------------------------------------------------------------------------------
- Trace Settings:
- -------------------------
- Trace Settings
- Peak Memory Usage: 865 MB
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