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spark watchdog config

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Feb 9th, 2014
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  1. #define __IWDG_PERIOD 0x01C9C380 // equals to 30000000 microseconds which should be 30 seconds
  2.  
  3. /*----------------------------------------------------------------------------
  4. Define IWDG PR and RLR settings and helps calculate the needed prescaler
  5. *----------------------------------------------------------------------------*/
  6. #if (__IWDG_PERIOD > 16384000UL)
  7. #define __IWDG_PR (6)
  8. #define __IWDGCLOCK (32000UL/256)
  9. #elif (__IWDG_PERIOD > 8192000UL)
  10. #define __IWDG_PR (5)
  11. #define __IWDGCLOCK (32000UL/128)
  12. #elif (__IWDG_PERIOD > 4096000UL)
  13. #define __IWDG_PR (4)
  14. #define __IWDGCLOCK (32000UL/64)
  15. #elif (__IWDG_PERIOD > 2048000UL)
  16. #define __IWDG_PR (3)
  17. #define __IWDGCLOCK (32000UL/32)
  18. #elif (__IWDG_PERIOD > 1024000UL)
  19. #define __IWDG_PR (2)
  20. #define __IWDGCLOCK (32000UL/16)
  21. #elif (__IWDG_PERIOD > 512000UL)
  22. #define __IWDG_PR (1)
  23. #define __IWDGCLOCK (32000UL/8)
  24. #else
  25. #define __IWDG_PR (0)
  26. #define __IWDGCLOCK (32000UL/4)
  27. #endif
  28. #define __IWGDCLK (32000UL/(0x04<<__IWDG_PR))
  29. #define __IWDG_RLR (__IWDG_PERIOD*__IWGDCLK/1000000UL-1)
  30.  
  31. void stm32_IwdgSetup () {
  32.  
  33. // RCC->CSR |= (1<<0); // LSI enable, necessary for IWDG
  34. // while ((RCC->CSR & (1<<1)) == 0); // wait till LSI is ready
  35.  
  36. IWDG->KR = 0x5555; // enable write to PR, RLR
  37. IWDG->PR = __IWDG_PR; // Init prescaler
  38. IWDG->RLR = __IWDG_RLR; // Init RLR
  39. IWDG->KR = 0xAAAA; // Reload the watchdog
  40. IWDG->KR = 0xCCCC; // Start the watchdog
  41. } // end of stm32_IwdgSetup
  42.  
  43. // DONT FORGET THIS!!!!! add this line to your main loop so that the watchdog gets reset
  44. IWDG->KR = 0xAAAA;
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