Creg

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity CReg is
    port (data: in std_logic_vector(11 downto 0);
            ld: in std_logic;
            rd: in std_logic;
            clk: in std_logic;
            mbit: out boolean;
            rdy: out boolean);
end entity CReg;

architecture behav of CReg is

type states is (STO, WT,RET);
signal newstate;

begin

-- state transition process
    process is
        variable currentstate: states := RET;
    begin
        if clk = '1' then
            case currentstate is
                when STO =>
                    currentstate := WT;
                when WT =>
                    if (ld = '1') then
                        currentstate := STO;
                    end if;

                    if not((ld = '1') or (rd = '1')) then
                        currentstate := WT;
                    end if;

                    if ld = '1' then
                        currentstate := STO;
                    end if;

                    if ((ld = '1') and (rd = '1')) then
                        currentstate := RET;
                    end if;
                when RET =>
                    currentstate := WT;
            end case;
            newstate <= currentstate;
        end if;
    wait on clk;
    end process;
-- asserted output process
    process is
        variable REG: std_logic_vector(11 downto 0);
        variable rdyVar: boolean := false;
        variable mbitVar: boolean := false;
    begin
        case newstate is
            when STO =>
                REG := data;
            when WT =>
                rdyVar := true;
            when RET =>
                mbitVar := (REG = data);
        end case;
        rdy <= rdyVar;
        mbit <= mbitVar;
    wait on newstate;
    end process;


end behav;