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Китайская SE8R01 спасибо пожалуйста инициализации

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  1. /******************************************************************************/
  2. /*                        -- ÉîÛÚ°²ÐſɿƼ¼ÓÐÏÞ¹«Ë¾ --                        */
  3. /*
  4. //  ÎļþÃû£º                                                              
  5. //  ËµÃ÷£º                                                                  
  6. //  ±àдÈËÔ±£º                                                                  
  7. //  ±àдÈÕÆÚ£º                                                              
  8. //  ³ÌÐòά»¤£º
  9. //  Î¬»¤¼Ç¼£º
  10. //
  11. //                                                          
  12. */
  13. // ÃâÔðÉùÃ÷£º¸Ã³ÌÐò½öÓÃÓÚѧϰÓë½»Á÷
  14. // (c) Anxinke Corporation. All rights reserved.                                                              
  15. /******************************************************************************/
  16. #include "typedef.h"
  17. #include <intrins.h>
  18. #include <string.h>
  19. #include "NRF_24L01.h"
  20. #include "UART.H"
  21. #include "delay.h"
  22.  
  23. #define uchar unsigned char
  24.  
  25.  
  26. uchar const TX_ADDRESS[TX_ADR_WIDTH]  = {0x34,0x43,0x10,0x10,0x01}; // Define a static TX address
  27. code unsigned char bank0_reg[][2]={
  28.     {0,0x0E},   // Interrupt reflected on the IRQ pin; Enable CRC; 2Byte; Poweron; PTX
  29.     {1,0x00},   // disenable auto ackknowledgement data
  30.     {2,0x01},   // enable pipe0
  31.     {3,0x02},   // 4Byte Address
  32.     {4,0x00},   // disable data Retransmission
  33.     {5,0x17},   // Frequency channel
  34.     {6,0x4F},   // 1Mbps; 0dBm; LNA
  35.     {28,0x01},  // pipe0 pipe1 enable dynamic payload length data
  36.     {29,0x07}   // enable dynamic paload lenght; enbale payload with ack enable w_tx_payload_noack
  37. };
  38.  
  39. idata uchar gtemp[5];
  40.  
  41. idata uchar rx_buf[TX_PLOAD_WIDTH];
  42.  
  43. idata uchar tx_buf[TX_PLOAD_WIDTH];
  44.  
  45. uchar flag;
  46.  
  47.  
  48.  
  49. /**************************************************/
  50.  
  51.  
  52.  
  53. //sbit LED1= P3^7;
  54. /**************************************************/
  55. unsigned char   bdata sta;
  56.  
  57. sbit    RX_DR   =sta^6;
  58.  
  59. sbit    TX_DS   =sta^5;
  60.  
  61. sbit    MAX_RT  =sta^4;
  62. /**************************************************/
  63.  
  64. /**************************************************
  65. Function: init_io();
  66. Description:
  67.   flash led one time,chip enable(ready to TX or RX Mode),
  68.   Spi disable,Spi clock line init high
  69. /**************************************************/
  70. #define KEY 0xaa
  71. void init_nrf24l01_io(void)
  72. {
  73.     CE=0;           // chip enable
  74.     CSN=1;          // Spi disable 
  75.     SCK=0;          // Spi clock line init high
  76. }
  77. /**************************************************
  78. Function: SPI_RW();
  79.  
  80. Description:
  81.   Writes one byte to nRF24L01, and return the byte read
  82.   from nRF24L01 during write, according to SPI protocol
  83. /**************************************************/
  84. bdata unsigned char st=0;
  85. sbit st_1=st^0;
  86. sbit st_2=st^1;
  87. sbit st_3=st^2;
  88. sbit st_4=st^3;
  89. sbit st_5=st^4;
  90. sbit st_6=st^5;
  91. sbit st_7=st^6;
  92. sbit st_8=st^7;
  93. bdata unsigned char st1=0;
  94. sbit st_11=st1^0;
  95. sbit st_12=st1^1;
  96. sbit st_13=st1^2;
  97. sbit st_14=st1^3;
  98. sbit st_15=st1^4;
  99. sbit st_16=st1^5;
  100. sbit st_17=st1^6;
  101. sbit st_18=st1^7;
  102. /*
  103. uchar SPI_RW(uchar byte)
  104. {
  105.     uchar bit_ctr;
  106.     for(bit_ctr=0;bit_ctr<8;bit_ctr++)   // output 8-bit
  107.     {
  108.         MOSI = (byte & 0x80);         // output 'byte', MSB to MOSI
  109.         byte = (byte << 1);           // shift next bit into MSB..
  110.         SCK = 1;                      // Set SCK high..
  111.         MISO=1;
  112.         byte |= MISO;                 // capture current MISO bit
  113.         SCK = 0;                      // ..then set SCK low again
  114.     }
  115.     return(byte);                     // return read byte
  116. }
  117. */
  118.  
  119. uchar SPI_RW(uchar byte)
  120. {
  121.     //uchar bit_ctr;
  122.  
  123.     st=byte;
  124.  
  125.     MOSI=st_8;
  126.     SCK = 1;
  127.     st_18=MISO;
  128.     SCK = 0;
  129.  
  130.     MOSI=st_7;
  131.     SCK = 1;
  132.     st_17=MISO;
  133.     SCK = 0;
  134.  
  135.     MOSI=st_6;
  136.     SCK = 1;
  137.     st_16=MISO;
  138.     SCK = 0;
  139.  
  140.     MOSI=st_5;
  141.     SCK = 1;
  142.     st_15=MISO;
  143.     SCK = 0;
  144.  
  145.     MOSI=st_4;
  146.     SCK = 1;
  147.     st_14=MISO;
  148.     SCK = 0;
  149.  
  150.     MOSI=st_3;
  151.     SCK = 1;
  152.     st_13=MISO;
  153.     SCK = 0;
  154.  
  155.     MOSI=st_2;
  156.     SCK = 1;
  157.     st_12=MISO;
  158.     SCK = 0;
  159.  
  160.     MOSI=st_1;
  161.     SCK = 1;
  162.     st_11=MISO;
  163.     SCK = 0;
  164.     return(st1);                  // return read byte
  165. }
  166. /**************************************************/
  167.  
  168. /**************************************************
  169. Function: SPI_RW_Reg();
  170.  
  171. Description:
  172.   Writes value 'value' to register 'reg'
  173. /**************************************************/
  174. uchar SPI_RW_Reg(BYTE reg, BYTE value)
  175. {
  176.     uchar status;
  177.     CSN = 0;                   // CSN low, init SPI transaction
  178.     status = SPI_RW(reg);      // select register
  179.     SPI_RW(value);             // ..and write value to it..
  180.     CSN = 1;                   // CSN high again
  181.     return(status);            // return nRF24L01 status byte
  182. }
  183. /**************************************************/
  184.  
  185. /**************************************************
  186. Function: SPI_Read();
  187.  
  188. Description:
  189.   Read one byte from nRF24L01 register, 'reg'
  190. /**************************************************/
  191. BYTE SPI_Read(BYTE reg)
  192. {
  193.     BYTE reg_val;
  194.  
  195.     CSN = 0;                // CSN low, initialize SPI communication...
  196.     SPI_RW(reg);            // Select register to read from..
  197.     reg_val = SPI_RW(0);    // ..then read registervalue
  198.     CSN = 1;                // CSN high, terminate SPI communication
  199.  
  200.     return(reg_val);        // return register value
  201. }
  202. /**************************************************/
  203.  
  204. /**************************************************
  205. Function: SPI_Read_Buf();
  206.  
  207. Description:
  208.   Reads 'bytes' #of bytes from register 'reg'
  209.   Typically used to read RX payload, Rx/Tx address
  210. /**************************************************/
  211. uchar SPI_Read_Buf(BYTE reg, BYTE *pBuf, BYTE bytes)
  212. {
  213.     uchar status,byte_ctr;
  214.  
  215.     CSN = 0;                            // Set CSN low, init SPI tranaction
  216.     status = SPI_RW(reg);               // Select register to write to and read status byte
  217.  
  218.     for(byte_ctr=0;byte_ctr<bytes;byte_ctr++)
  219.         pBuf[byte_ctr] = SPI_RW(0);    // Perform SPI_RW to read byte from nRF24L01
  220.  
  221.     CSN = 1;                           // Set CSN high again
  222.  
  223.     return(status);                    // return nRF24L01 status byte
  224. }
  225. /**************************************************/
  226.  
  227. /**************************************************
  228. Function: SPI_Write_Buf();
  229.  
  230. Description:
  231.   Writes contents of buffer '*pBuf' to nRF24L01
  232.   Typically used to write TX payload, Rx/Tx address
  233. /**************************************************/
  234. uchar SPI_Write_Buf(BYTE reg, BYTE *pBuf, BYTE bytes)
  235. {
  236.     uchar status,byte_ctr;
  237.  
  238.     CSN = 0;                   // Set CSN low, init SPI tranaction
  239.     status = SPI_RW(reg);    // Select register to write to and read status byte
  240.     for(byte_ctr=0; byte_ctr<bytes; byte_ctr++) // then write all byte in buffer(*pBuf)
  241.         SPI_RW(*pBuf++);
  242.     CSN = 1;                 // Set CSN high again
  243.     return(status);          // return nRF24L01 status byte
  244. }
  245. /**************************************************/
  246.  
  247. /**************************************************
  248. Function: RX_Mode();
  249.  
  250. Description:
  251.   This function initializes one nRF24L01 device to
  252.   RX Mode, set RX address, writes RX payload width,
  253.   select RF channel, datarate & LNA HCURR.
  254.   After init, CE is toggled high, which means that
  255.   this device is now ready to receive a datapacket.
  256. /**************************************************/
  257. void power_off()
  258. {
  259.     CE=0;
  260.     SPI_RW_Reg(WRITE_REG + CONFIG, 0x0D);
  261.     CE=1;
  262.     _delay_us(20);
  263. }
  264. void ifnnrf_rx_mode(void)
  265. {
  266.     power_off();
  267.     CE=0;
  268.     SPI_Write_Buf(WRITE_REG + RX_ADDR_P0, TX_ADDRESS, TX_ADR_WIDTH); // Use the same address on the RX device as the TX device
  269.     SPI_RW_Reg(iRF_CMD_WRITE_REG|iRF_BANK0_STATUS,0x70);
  270.  
  271.     SPI_RW_Reg(WRITE_REG + EN_AA, 0x01);      // Enable Auto.Ack:Pipe0
  272.     SPI_RW_Reg(WRITE_REG + EN_RXADDR, 0x01);  // Enable Pipe0
  273.     SPI_RW_Reg(WRITE_REG + RF_CH, 40);        // Select RF channel 40
  274.     SPI_RW_Reg(WRITE_REG + RX_PW_P0, TX_PLOAD_WIDTH); // Select same RX payload width as TX Payload width
  275.     SPI_RW_Reg(WRITE_REG + RF_SETUP, 0x4f);   // TX_PWR:0dBm, Datarate:2Mbps, LNA:HCURR
  276.     SPI_RW_Reg(WRITE_REG + CONFIG, 0x0f);     // Set PWR_UP bit, enable CRC(2 bytes) & Prim:RX. RX_DR enabled..
  277.  
  278.     CE = 1; // Set CE pin high to enable RX device
  279.  
  280.   //  This device is now ready to receive one packet of 16 bytes payload from a TX device sending to address
  281.   //  '3443101001', with auto acknowledgment, \retransmit count of 10, RF channel 40 and datarate = 2Mbps.
  282.  
  283. }
  284. /**************************************************/
  285.  
  286. /**************************************************
  287. Function: TX_Mode();
  288.  
  289. Description:
  290.   This function initializes one nRF24L01 device to
  291.   TX mode, set TX address, set RX address for auto.ack,
  292.   fill TX payload, select RF channel, datarate & TX pwr.
  293.   PWR_UP is set, CRC(2 bytes) is enabled, & PRIM:TX.
  294.  
  295.   ToDo: One high pulse(>10us) on CE will now send this
  296.   packet and expext an acknowledgment from the RX device.
  297. /**************************************************/
  298.  
  299. void rf_switch_bank(unsigned char bankindex)
  300. {
  301.     unsigned char temp0,temp1;
  302.     temp1 = bankindex;
  303.  
  304.     temp0 = SPI_RW(iRF_BANK0_STATUS);
  305.  
  306.     if((temp0&0x80)!=temp1)
  307.     {
  308.         SPI_RW_Reg(iRF_CMD_ACTIVATE,0x53);
  309.     }
  310. }
  311.  
  312. void ifnnrf_tx_mode(void)
  313. {
  314.     power_off();
  315.     CE=0;
  316.     SPI_RW_Reg(iRF_CMD_WRITE_REG|iRF_BANK0_STATUS,0x70);
  317.    
  318.     SPI_Write_Buf(WRITE_REG + TX_ADDR, TX_ADDRESS, TX_ADR_WIDTH);    // Writes TX_Address to nRF24L01
  319.     SPI_Write_Buf(WRITE_REG + RX_ADDR_P0, TX_ADDRESS, TX_ADR_WIDTH); // RX_Addr0 same as TX_Adr for Auto.Ack
  320.     SPI_Write_Buf(WR_TX_PLOAD, tx_buf, TX_PLOAD_WIDTH); // Writes data to TX payload
  321.  
  322.     SPI_RW_Reg(WRITE_REG + EN_AA, 0x01);      // Enable Auto.Ack:Pipe0
  323.     SPI_RW_Reg(WRITE_REG + EN_RXADDR, 0x01);  // Enable Pipe0
  324.     SPI_RW_Reg(WRITE_REG + SETUP_RETR, 0x1a); // 500us + 86us, 10 retrans...
  325.     SPI_RW_Reg(WRITE_REG + RF_CH, 40);        // Select RF channel 40
  326.     SPI_RW_Reg(WRITE_REG + RF_SETUP, 0x4f);   // TX_PWR:0dBm, Datarate:2Mbps, LNA:HCURR
  327.     SPI_RW_Reg(WRITE_REG + CONFIG, 0x0e);     // Set PWR_UP bit, enable CRC(2 bytes) & Prim:TX. MAX_RT & TX_DS enabled..
  328.     CE=1;
  329.  
  330. }
  331.  
  332. void SPI_CLR_Reg(BYTE R_T)
  333. {
  334.     CSN = 0;
  335.     if(R_T==1)                  // CSN low, init SPI transaction
  336.     SPI_RW(FLUSH_TX);             // ..and write value to it..
  337.     else
  338.     SPI_RW(FLUSH_RX);             // ..and write value to it..
  339.     CSN = 1;                   // CSN high again
  340. }
  341.  
  342. void ifnnrf_CLERN_ALL()
  343. {
  344.   SPI_CLR_Reg(0);
  345.   SPI_CLR_Reg(1);
  346.   SPI_RW_Reg(WRITE_REG+STATUS,0xff);
  347.   IRQ=1;
  348. }
  349. void rf_init(void)
  350. {
  351.     unsigned char i,j;
  352.  
  353.     CE=0;//mRF_CE_LOW_TX;
  354.     delay_us(50);                            \
  355.  
  356.     for(j=0; j<3; j++)
  357.     {
  358. // se8r01_powerup_calibration();
  359.         rf_switch_bank(iBANK0);
  360.         SPI_RW_Reg(iRF_CMD_WRITE_REG|iRF_BANK0_CONFIG,0x03);
  361.         SPI_RW_Reg(iRF_CMD_WRITE_REG|iRF_BANK0_RF_CH,0x32);
  362.         SPI_RW_Reg(iRF_CMD_WRITE_REG|iRF_BANK0_RF_SETUP,0x48);
  363.         SPI_RW_Reg(iRF_CMD_WRITE_REG|iRF_BANK0_PRE_GURD,0x77); //2450 calibration
  364.  
  365.         rf_switch_bank(iBANK1);
  366.  
  367.         gtemp[0]=0x40;
  368.         gtemp[1]=0x00;
  369.         gtemp[2]=0x10;
  370.         gtemp[3]=0xE6;
  371.         SPI_Write_Buf(iRF_CMD_WRITE_REG|iRF_BANK1_PLL_CTL0, gtemp, 4);
  372.  
  373.         gtemp[0]=0x20;
  374.         gtemp[1]=0x08;
  375.         gtemp[2]=0x50;
  376.         gtemp[3]=0x40;
  377.         gtemp[4]=0x50;
  378.         SPI_Write_Buf(iRF_CMD_WRITE_REG|iRF_BANK1_CAL_CTL, gtemp, 5);
  379.  
  380.         gtemp[0]=0x00;
  381.         gtemp[1]=0x00;
  382.         gtemp[2]=0x1E;
  383.         SPI_Write_Buf(iRF_CMD_WRITE_REG|iRF_BANK1_IF_FREQ, gtemp, 3);
  384.  
  385.         gtemp[0]=0x29;
  386.         SPI_Write_Buf(iRF_CMD_WRITE_REG|iRF_BANK1_FDEV, gtemp, 1);
  387.  
  388.         gtemp[0]=0x00;
  389.         SPI_Write_Buf(iRF_CMD_WRITE_REG|iRF_BANK1_DAC_CAL_LOW, gtemp, 1);
  390.  
  391.         gtemp[0]=0x7F;
  392.         SPI_Write_Buf(iRF_CMD_WRITE_REG|iRF_BANK1_DAC_CAL_HI, gtemp, 1);
  393.  
  394.         gtemp[0]=0x02;
  395.         gtemp[1]=0xC1;
  396.         gtemp[2]=0xEB;
  397.         gtemp[3]=0x1C;
  398.         SPI_Write_Buf(iRF_CMD_WRITE_REG|iRF_BANK1_AGC_GAIN, gtemp, 4);
  399.  
  400.         gtemp[0]=0x97;
  401.         gtemp[1]=0x64;
  402.         gtemp[2]=0x00;
  403.         gtemp[3]=0x81;
  404.         SPI_Write_Buf(iRF_CMD_WRITE_REG|iRF_BANK1_RF_IVGEN, gtemp, 4);
  405.  
  406.         rf_switch_bank(iBANK0);
  407.  
  408.         CE=1;//mRF_CE_HIGH_TX;
  409.         delay_us(30);
  410.         CE=0;
  411.  
  412.         delay_ms(50);                            // delay 50ms waitting for calibaration.
  413.  
  414.         CE=1;//mRF_CE_HIGH_TX;
  415.         delay_us(30);
  416.         CE=0;//mRF_CE_LOW_TX;
  417.  
  418.         delay_ms(50);                            // delay 50ms waitting for calibaration.
  419. // calibration end
  420.  
  421.         for(i=0;i<9;i++)
  422.         {
  423.             SPI_RW_Reg((iRF_CMD_WRITE_REG|bank0_reg[i][0]),bank0_reg[i][1]);
  424.         }
  425.  
  426.         gtemp[0]=0x28;
  427.         gtemp[1]=0x32;
  428.         gtemp[2]=0x80;
  429.         gtemp[3]=0x90;
  430.         gtemp[4]=0x00;
  431.         SPI_Write_Buf(iRF_CMD_WRITE_REG|iRF_BANK0_SETUP_VALUE, gtemp, 5);
  432.  
  433.         delay_ms(2);
  434.  
  435.         rf_switch_bank(iBANK1);
  436.  
  437.         gtemp[0]=0x40;
  438.         gtemp[1]=0x01;
  439.         gtemp[2]=0x30;
  440.         gtemp[3]=0xE2;
  441.         SPI_Write_Buf(iRF_CMD_WRITE_REG|iRF_BANK1_PLL_CTL0, gtemp, 4);
  442.  
  443.         gtemp[0]=0x29;
  444.         gtemp[1]=0x89;
  445.         gtemp[2]=0x55;
  446.         gtemp[3]=0x40;
  447.         gtemp[4]=0x50;
  448.         SPI_Write_Buf(iRF_CMD_WRITE_REG|iRF_BANK1_CAL_CTL, gtemp, 5);
  449.  
  450.         gtemp[0]=0x29;
  451.         SPI_Write_Buf(iRF_CMD_WRITE_REG|iRF_BANK1_FDEV, gtemp, 1);
  452.  
  453.         gtemp[0]=0x55;
  454.         gtemp[1]=0xC2;
  455.         gtemp[2]=0x09;
  456.         gtemp[3]=0xAC;
  457.         SPI_Write_Buf(iRF_CMD_WRITE_REG|iRF_BANK1_RX_CTRL, gtemp, 4);
  458.  
  459.         gtemp[0]=0x00;
  460.         gtemp[1]=0x14;
  461.         gtemp[2]=0x08;
  462.         gtemp[3]=0x29;
  463.         SPI_Write_Buf(iRF_CMD_WRITE_REG|iRF_BANK1_FAGC_CTRL_1, gtemp, 4);
  464.  
  465.         gtemp[0]=0x02;
  466.         gtemp[1]=0xC1;
  467.         gtemp[2]=0xCB;
  468.         gtemp[3]=0x1C;
  469.         SPI_Write_Buf(iRF_CMD_WRITE_REG|iRF_BANK1_AGC_GAIN, gtemp, 4);
  470.  
  471.         gtemp[0]=0x97;
  472.         gtemp[1]=0x64;
  473.         gtemp[2]=0x00;
  474.         gtemp[3]=0x01;
  475.         SPI_Write_Buf(iRF_CMD_WRITE_REG|iRF_BANK1_RF_IVGEN, gtemp, 4);
  476.  
  477.         gtemp[0]=0x2A;
  478.         gtemp[1]=0x04;
  479.         gtemp[2]=0x00;
  480.         gtemp[3]=0x7D;
  481.         SPI_Write_Buf(iRF_CMD_WRITE_REG|iRF_BANK1_TEST_PKDET, gtemp, 4);
  482.  
  483.         rf_switch_bank(iBANK0);
  484.  
  485. // rf testself
  486.         //brf_status_error = 0;
  487.         if(0x17 == SPI_RW(iRF_BANK0_RF_CH))
  488.         {
  489.             SPI_RW_Reg(iRF_CMD_WRITE_REG|iRF_BANK0_STATUS,0x70);
  490.  
  491.             if(IRQ)
  492.             {
  493.                 CE=1;//mRF_CE_HIGH_TX;
  494.                 //rf_write_fifo(1); -------------------------------------------------------------
  495.                 delay_ms(1);
  496.                 if(IRQ==0)
  497.                 {
  498.                     CE=0;//mRF_CE_LOW_TX;
  499.                     SPI_RW_Reg(iRF_CMD_WRITE_REG|iRF_BANK0_STATUS,0x70);
  500.                     return;
  501.                 }
  502.                 CE=0;//mRF_CE_LOW_TX;
  503.                 SPI_RW_Reg(iRF_CMD_WRITE_REG|iRF_BANK0_STATUS,0x70);
  504.             }
  505.         }
  506.         ;
  507.         //brf_status_error = 1;
  508.     }
  509. }
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