Jan 28 16:58:18 stonehenge kernel: Booting Linux on physical CPU 0xa00
Jan 28 16:58:18 stonehenge kernel: Initializing cgroup subsys cpuset
Jan 28 16:58:18 stonehenge kernel: Initializing cgroup subsys cpu
Jan 28 16:58:18 stonehenge kernel: Linux version 3.8.13.30 (root@xu-b1) (gcc version 4.7.3 (Ubuntu/Linaro 4.7.3-12ubuntu1) ) #1 SMP PREEMPT Fri
Jan 28 16:58:18 stonehenge kernel: Kernel was built at commit id '698c7ea'
Jan 28 16:58:18 stonehenge kernel: CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=10c5387d
Jan 28 16:58:18 stonehenge kernel: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
Jan 28 16:58:18 stonehenge kernel: Machine: ODROID-U2/U3
Jan 28 16:58:18 stonehenge kernel: cma: CMA: reserved 64 MiB at 43000000
Jan 28 16:58:18 stonehenge kernel: cma: CMA: reserved 64 MiB at 51000000
Jan 28 16:58:18 stonehenge kernel: cma: CMA: reserved 128 MiB at 67800000
Jan 28 16:58:18 stonehenge kernel: Memory policy: ECC disabled, Data cache writealloc
Jan 28 16:58:18 stonehenge kernel: CPU EXYNOS4412 (id 0xe4412220)
Jan 28 16:58:18 stonehenge kernel: exynos4_init_clocks: initializing clocks
Jan 28 16:58:18 stonehenge kernel: S3C24XX Clocks, Copyright 2004 Simtec Electronics
Jan 28 16:58:18 stonehenge kernel: s3c_register_clksrc: clock armclk has no registers set
Jan 28 16:58:18 stonehenge kernel: s3c_register_clksrc: clock audiocdclk has no registers set
Jan 28 16:58:18 stonehenge kernel: audiocdclk: no parent clock specified
Jan 28 16:58:18 stonehenge kernel: exynos4_setup_clocks: registering clocks
Jan 28 16:58:18 stonehenge kernel: exynos4_setup_clocks: xtal is 24000000
Jan 28 16:58:18 stonehenge kernel: EXYNOS4: PLL settings, A=1000000000, M=880000000, E=96000000 V=350000000
Jan 28 16:58:18 stonehenge kernel: EXYNOS4: ARMCLK=1000000000, DMC=440000000, ACLK200=176000000
                                   ACLK100=110000000, ACLK160=176000000, ACLK133=146666666
Jan 28 16:58:18 stonehenge kernel: sclk_pwm: source is ext_xtal (0), rate is 24000000
Jan 28 16:58:18 stonehenge kernel: sclk_csis: source is xusbxti (1), rate is 1500000
Jan 28 16:58:18 stonehenge kernel: sclk_csis: source is xusbxti (1), rate is 1500000
Jan 28 16:58:18 stonehenge kernel: sclk_cam0: source is xusbxti (1), rate is 1500000