#define SW_SDRAM_BASE		0x01c01000
#define SW_SDRAM_BASE_LEN	0x100

#define SW_SDRAM_REG_HPCR_USB1	(0x250 + ((1 << 2) * 4))
#define SW_SDRAM_REG_HPCR_USB2	(0x250 + ((1 << 2) * 5))

/* HPCR */
#define SW_SDRAM_BP_HPCR_READ_CNT_EN		31
#define SW_SDRAM_BP_HPCR_RWRITE_CNT_EN		30
#define SW_SDRAM_BP_HPCR_COMMAND_NUM		8
#define SW_SDRAM_BP_HPCR_WAIT_STATE		4
#define SW_SDRAM_BP_HPCR_PRIORITY_LEVEL		2
#define SW_SDRAM_BP_HPCR_ACCESS_EN		0