simple tcl examples (c) Mentor Graphics

# (c) Mentor Graphics modelsim_tcl.pdf


#-----
#    Tcl while Loop
# This example uses the Tcl while loop to copy a list from variable a to variable b, reversing the order of the
# elements along the way:

set b [list]
set i [expr {[llength $a] - 1}]
while {$i >= 0} {
   lappend b [lindex $a $i]
   incr i -1
}

#-----
#    Tcl for Command
# This example uses the Tcl for command to copy a list from variable a to variable b, reversing the order of the
# elements along the way:

set b [list]
for {set i [expr {[llength $a] - 1}]} {$i >= 0} {incr i -1} {
   lappend b [lindex $a $i]
}

#-----
#    Tcl foreach Command

# This example uses the Tcl foreach command to copy a list from variable a to variable b, reversing the order of the # elements along the way (the foreach command iterates over all of the elements of a list):

set b [list]
foreach i $a { set b [linsert $b 0 $i] }

#-----
#    Tcl break Command

# This example shows a list reversal as above, this time aborting on a particular element using the Tcl break command:

set b [list]
foreach i $a {
   if {$i = "ZZZ"} break
   set b [linsert $b 0 $i]
}

#-----
#    Tcl continue Command

# This example is a list reversal that skips a particular element by using the Tcl continue command:

set b [list]
foreach i $a {
   if {$i = "ZZZ"} continue
   set b [linsert $b 0 $i]
}

#-----
#    Access and Transfer System Information

# This example works in UNIX only. In a Windows environment, the Tcl exec command will execute compiled files only,
# not system     --sets the breakpoint to call set_datecommands.) The example shows how you can access system information and transfer it into VHDL variables
# or signals and Verilog nets or registers. When a particular HDL source breakpoint occurs, a Tcl function is called # that #gets the date and time and deposits it into a VHDL signal of type STRING. If a particular environment
# variable (DO_ECHO) is set, the function also echoes the new date and time to the transcript file by examining the #  VHDL variable.

# (in VHDL source):
# signal datime : string(1 to 28) := " ";
# (on VSIM command line or in a DO file script):

proc set_date {} {
   global env
   set do_the_echo [set env(DO_ECHO)]
   set s [clock format [clock seconds]]
   force -deposit datime $s
   if {do_the_echo} {
      echo "New time is [examine -value datime]"
   }
}

bp src/waveadd.vhd 133 {set_date; continue}
#    --sets the breakpoint to call set_date

#-----
#    Tcl Used to Specify Compiler Arguments

# This example specifies the compiler arguments and lets you compile any number of files.

set Files [list]
set nbrArgs $argc
for {set x 1} {$x <= $nbrArgs} {incr x} {
   set lappend Files $1
   shift
}
eval vcom -93 -explicit -noaccel std_logic_arith $Files

#-----
#    Tcl Used to Specify Compiler Arguments—Enhanced

# This example is an enhanced version of the last one. The additional code determines whether the files are VHDL or   # Verilog and uses the appropriate compiler and arguments depending on the file type. Note that the script assumes
# your VHDL files have a .vhd file extension.

set vhdFiles [list]
set vFiles [list]
set nbrArgs $argc
for {set x 1} {$x <= $nbrArgs} {incr x} {
   if {[string match *.vhd $1]} {
      lappend vhdFiles $1
   } else {
      lappend vFiles $1
   }
   shift
}
if {[llength $vhdFiles] > 0} {
   eval vcom -93 -explicit -noaccel std_logic_arith $vhdFiles
}
if {[llength $vFiles] > 0} {
   eval vlog $vFiles
}