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  1. library IEEE;
  2. use IEEE.std_logic_1164.all; -- defines std_logic types
  3. use IEEE.STD_LOGIC_ARITH.ALL;
  4. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  5.  
  6. -- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
  7. -- http://www.mesanet.com
  8. --
  9. -- This program is is licensed under a disjunctive dual license giving you
  10. -- the choice of one of the two following sets of free software/open source
  11. -- licensing terms:
  12. --
  13. -- * GNU General Public License (GPL), version 2.0 or later
  14. -- * 3-clause BSD License
  15. --
  16. --
  17. -- The GNU GPL License:
  18. --
  19. -- This program is free software; you can redistribute it and/or modify
  20. -- it under the terms of the GNU General Public License as published by
  21. -- the Free Software Foundation; either version 2 of the License, or
  22. -- (at your option) any later version.
  23. --
  24. -- This program is distributed in the hope that it will be useful,
  25. -- but WITHOUT ANY WARRANTY; without even the implied warranty of
  26. -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  27. -- GNU General Public License for more details.
  28. --
  29. -- You should have received a copy of the GNU General Public License
  30. -- along with this program; if not, write to the Free Software
  31. -- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  32. --
  33. --
  34. -- The 3-clause BSD License:
  35. --
  36. -- Redistribution and use in source and binary forms, with or without
  37. -- modification, are permitted provided that the following conditions
  38. -- are met:
  39. --
  40. -- * Redistributions of source code must retain the above copyright
  41. -- notice, this list of conditions and the following disclaimer.
  42. --
  43. -- * Redistributions in binary form must reproduce the above
  44. -- copyright notice, this list of conditions and the following
  45. -- disclaimer in the documentation and/or other materials
  46. -- provided with the distribution.
  47. --
  48. -- * Neither the name of Mesa Electronics nor the names of its
  49. -- contributors may be used to endorse or promote products
  50. -- derived from this software without specific prior written
  51. -- permission.
  52. --
  53. --
  54. -- Disclaimer:
  55. --
  56. -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  57. -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  58. -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  59. -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
  60. -- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  61. -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  62. -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  63. -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  64. -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  65. -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  66. -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  67. -- POSSIBILITY OF SUCH DAMAGE.
  68. --
  69.  
  70. use work.IDROMConst.all;
  71.  
  72. package MYPINS0 is
  73. constant ModuleID : ModuleIDType :=(
  74. (WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
  75. (IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
  76. (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
  77. (StepGenTag, x"02", ClockLowTag, x"08", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
  78. (PWMTag, x"00", ClockHighTag, x"02", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
  79. (LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
  80. (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
  81. (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
  82. (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
  83. (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
  84. (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
  85. (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
  86. (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
  87. (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
  88. (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
  89. (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
  90. (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
  91. (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
  92. (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
  93. (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
  94. (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
  95. (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
  96. (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
  97. (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
  98. (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
  99. (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
  100. (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
  101. (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
  102. (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
  103. (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
  104. (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
  105. (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
  106. );
  107.  
  108.  
  109. constant PinDesc : PinDescType :=(
  110. -- Base func sec unit sec func sec pin -- external DB25
  111. IOPortTag & x"00" & NullTag & NullPin, -- I/O 00 PIN 1 Output 2 just GPIO
  112. IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 01 PIN 14 Spindle DAC PWM
  113. IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 02 PIN 2 X 1
  114. IOPortTag & x"00" & NullTag & NullPin, -- I/O 03 PIN 15 just GPIO
  115. IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 04 PIN 3 X 2
  116. IOPortTag & x"00" & PWMTag & PWMBDirPin, -- I/O 05 PIN 16 Spindle DAC Dir
  117. IOPortTag & x"00" & StepGenTag & StepGenTable2Pin, -- I/O 06 PIN 4 X 3
  118. IOPortTag & x"00" & NullTag & NullPin, -- I/O 07 PIN 17 Output 1 just GPIO
  119. IOPortTag & x"00" & StepGenTag & StepGenTable3Pin, -- I/O 08 PIN 5 X 4
  120. IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 09 PIN 6 Y 1
  121. IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 10 PIN 7 Y 2
  122. IOPortTag & x"01" & StepGenTag & StepGenTable2Pin, -- I/O 11 PIN 8 Y 3
  123. IOPortTag & x"01" & StepGenTag & StepGenTable3Pin, -- I/O 12 PIN 9 Y 4
  124. IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 13 PIN 10 Z 1
  125. IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 14 PIN 11 Z 2
  126. IOPortTag & x"02" & StepGenTag & StepGenTable2Pin, -- I/O 15 PIN 12 Z 3
  127. IOPortTag & x"02" & StepGenTag & StepGenTable3Pin, -- I/O 16 PIN 13 Z 4
  128.  
  129. -- 26 HDR -- IDC DB25
  130. IOPortTag & x"00" & NullTag & NullPin, -- I/O 17 PIN 1 PIN 1 Output 2 just GPIO
  131. IOPortTag & x"01" & PWMTag & PWMAOutPin, -- I/O 18 PIN 2 PIN 14 Spindle DAC PWM
  132. IOPortTag & x"00" & NullTag & NullPin, -- I/O 19 PIN 3 PIN 2 Input 4 just GPIO
  133. IOPortTag & x"00" & NullTag & NullPin, -- I/O 20 PIN 4 PIN 15 just GPIO
  134. emptypin, -- I/O 21 PIN 5 PIN 3 X2 Dir
  135. IOPortTag & x"01" & PWMTag & PWMBDirPin, -- I/O 22 PIN 6 PIN 16 Spindle DAC DirHz)
  136. emptypin, -- I/O 23 PIN 7 PIN 4 Y2 Step
  137. IOPortTag & x"00" & NullTag & NullPin, -- I/O 24 PIN 8 PIN 17 Output 1 just GPIO
  138. emptypin, -- I/O 25 PIN 9 PIN 5 Y2 Dir
  139. emptypin, -- I/O 26 PIN 11 PIN 6 Z2 Step
  140. emptypin, -- I/O 27 PIN 13 PIN 7 Z2 Dir
  141. emptypin, -- I/O 28 PIN 15 PIN 8 A2 Step
  142. emptypin, -- I/O 29 PIN 17 PIN 9 A2 Dir
  143. IOPortTag & x"00" & NullTag & NullPin, -- I/O 30 PIN 19 PIN 10 Input 4 just GPIO
  144. emptypin, -- I/O 31 PIN 21 PIN 11 Input 2 (Quad A)
  145. emptypin, -- I/O 32 PIN 23 PIN 12 Input 3 (Quad B))
  146. emptypin, -- I/O 33 PIN 25 PIN 13 Input 4 (Quad Idx)
  147.  
  148.  
  149. emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for 34 pin 5I25
  150. emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
  151.  
  152.  
  153. emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
  154. emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
  155.  
  156. emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
  157. emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
  158. emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
  159. emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
  160. emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
  161. emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
  162. emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
  163. emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
  164. emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
  165. emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
  166.  
  167. end package MYPINS0;
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