GD_EMU DMA (OzOnE) 8-12-11

// Note: "cf_state" normally sits at state 7 after the CF card is initialized... The main GD part of the code kicks off the DMA transfer by setting "cf_state" to 8 after "gd_start_sector" and "gd_sector_count" parameters have been grabbed...


8: begin
    cf_lba <= ((gd_start_sector - 32'd45150) * 4) + 32'd45150;  // Need to multiply the sector offset by 4 (starting from the track offset).
    cf_sec_count_32 <= {gd_sector_count[29:0], 2'b00};  // GD-ROM sectors are normally 2048 bytes instead of 512, so need to multiply by 4.
    cf_state <= 10'd9;
end

9: begin
    cf_addr <= 3'h07;               // Select Command / Status reg.
    cf_rd_n_reg <= 1'b0;            // Assert IDE Read...
    if (~cf_data[7] && cf_data[6]) begin // Wait until BUSY bit goes low and DRDY bit goes high...
        cf_rd_n_reg <= 1'b1;            // De-assert IDE Read.
        cf_state <= 10'd10;
    end
end

10: begin
        if (cf_sec_count_32 >= 32'd256) begin
            cf_sec_count <= 8'h00;              // Transfer 256 sectors for this block (CF transfers 256 sectors when sec_count == 0!).
            cf_data_write <= 8'h00;             // Write sector count to drive.
        end
        else begin                                  // Else, 255 (or less) sectors left to transfer...
            cf_sec_count <= cf_sec_count_32[7:0];   // Use lower 8 bits of 32-bit sector count for the CF card (hacky)...
            cf_data_write <= cf_sec_count_32[7:0];  // Write sector count to drive.
        end
    cf_addr <= 3'h02;                       // Select "Sector Count" reg.
    cf_wr_n_reg <= 1'b0;                    // Pulse IDE WRite pin.
    cf_state <= 10'd11;
end

11: begin
    cf_wr_n_reg <= 1'b1;        // De-assert IDE WRite pin (data latched on RISING edge!).
    cf_state <= 10'd12;
end

// Next part of code (cf_state 12 to 19) not shown for clarity - all it does it write the LBA values to the CF card. Should be working OK...


20: begin
    cf_addr <= 3'h07;               // Select Command / Status reg.
    cf_rd_n_reg <= 1'b0;            // Assert IDE Read...
    cf_state <= 10'd21;
end

21:if (~cf_data[7] && cf_data[6]) begin // Wait until BUSY bit goes low and DRDY bit goes high...
        cf_rd_n_reg <= 1'b1;            // De-assert IDE Read.
        cf_addr <= 3'h07;           // Select Command / Status reg.
//      cf_data_write <= 8'h20;     // Send "Read Sector(s)" (PIO) command.
        cf_data_write <= 8'hC8;     // Send "Read DMA" command.
        cf_wr_n_reg <= 1'b0;        // Pulse IDE WRite pin.
        cf_state <= 10'd22;
    end

22: begin
    cf_wr_n_reg <= 1'b1;        // De-assert IDE WRite pin (data latched on RISING edge!).
    cf_state <= 10'd24;
end

24: //if (cf_dma_rq == 1'b1 && cf_data[3]) begin        // Wait for DRQ (Data ready for transfer) high.
    begin
//  cf_rd_n_reg <= 1'b1;                    // De-assert read.
    cf_wordcount <= 8'd0;                   // Start "cf_wordcount" at zero (will wrap, then decrement after each transfer).
    cf_addr <= 8'h00;                       // Zero the CF address pins (ready for DMA transfer).
    cf_state <= 10'd25;
end

25: begin
        if (gd_rd_falling) begin                            // If "gd_dma_ack_n" is asserted, on rising edge of "gd_rd_n"...
            cf_wordcount <= cf_wordcount + 8'd1;        // Increment word count (WORD just transferred via DMA).
                                                        // Note: "gd_rd_n" drives "cf_rd_n" when "gd_dma_ack_n" is asserted (during DMA!).
            if (cf_wordcount == 8'd255) begin
                cf_sec_count <= cf_sec_count - 8'd1;        // Decrement sector count when wordcount == 255 (driven by "gd_rd_rising"!)
                cf_sec_count_32 <= cf_sec_count_32 - 32'd1;
                cf_lba <= cf_lba + 32'd1;                   // Increment LBA ready for the next block (if there is one!).
            end
        end

        if (gd_rd_rising) begin
            if (cf_sec_count == 8'h00) cf_state <= 10'd26;  // Finished current block when sector count is zero...
        end
end

26: if (cf_sec_count_32 == 0) begin     // Have all sectors been transferred?...
        gds_procpacketdone();           // Yes, Will also set "gd_state" back to idle.
        cf_state <= 10'd7;              // All sectors transferred! - back to idle.
    end
    else begin
        cf_state <= 10'd9;              // Still more sectors left to transfer, loop!
    end