library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity pomreg is
    Port ( iARITH : in  STD_LOGIC;
           iLOAD : in  STD_LOGIC;
           iDATA : in  STD_LOGIC_VECTOR (7 downto 0);
           iSHL : in  STD_LOGIC;
           iSHR : in  STD_LOGIC;
           iCLK : in  STD_LOGIC;
           inRST : in  STD_LOGIC;
           oSHREG : out  STD_LOGIC_VECTOR (7 downto 0));
end pomreg;

architecture Behavioral of pomreg is
signal sREG: std_logic_vector(7 downto 0);

begin

process(iCLK, inRST) begin
    if(inRST = '0') then
        sREG<="00000000";
    elsif(iCLK'event and iCLK = '1') then
        if(iLOAD = '1') then
            sREG<=iDATA;
        elsif(iSHL = '1') then
            if iSHR = '1' then sREG <= sREG;
            else
            sREG<=iDATA(6 downto 0) & '0';
            end if;
        elsif(iSHR = '1') then
            if iSHL = '1' then sREG <=sREG;
            else
            if (iARITH = '1') then
                sREG<=iDATA(7) & '0' & iDATA(6 downto 1);
            else sREG<='0' & iDATA(7 downto 1);
            end if;
            end if;
    end if;
    end if;
end process;

oSHREG<=sREG;

end Behavioral;