API tools faq
paste
Advertisement
Guest User

Untitled

a guest
May 25th, 2015
224
0
Never
Add comment
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
text 12.26 KB | None | 0 0
raw download clone embed print report
  1. #include <assert.h>
  2. #include <stdio.h>
  3. #include <stdlib.h>
  4. #include <string.h>
  5. #include <pthread.h>
  6.  
  7. #define X_INSTRUCTIONS_NOT_NEEDED
  8.  
  9. #include "xis.h"
  10. #include "xcpu.h"
  11.  
  12. #define false 0
  13. #define true 1
  14.  
  15. void xcpu_print( xcpu *c ) {
  16. int i;
  17.  
  18. fprintf( stdout, "PC: %4.4x, State: %4.4x: Registers:\n", c->pc, c->state );
  19. for( i = 0; i < X_MAX_REGS; i++ ) {
  20. fprintf( stdout, " %4.4x", c->regs[i] );
  21. }
  22. fprintf( stdout, "\n" );
  23. }
  24.  
  25. extern int xcpu_execute( xcpu *c ) {
  26. unsigned short OP1;
  27. unsigned short OP2;
  28. unsigned short S;
  29. unsigned short D;
  30. unsigned short L;
  31. unsigned short a;
  32. unsigned short item1;
  33. unsigned short item2;
  34. int status = true;
  35.  
  36. //Fetch two bytes of the records
  37. OP1 = c->memory[(c->pc)]; //This is the high byte
  38. OP2 = c->memory[(c->pc+1)]; //This is the low byte
  39. c->pc = c->pc + 2; //General incrementation of the PC
  40.  
  41. //Execute + Increment the PC
  42. switch ((XIS_OPS&OP1)>>6){
  43. case 0x00: // OPS OPNUM Operations with no operands
  44. switch(OP1){
  45. case I_BAD:
  46. status = false;
  47. break;
  48. case I_RET:
  49. item1 = c->memory[c->regs[15]];
  50. item2 = c->memory[c->regs[15]+1];
  51. c->pc = (item1 << 8)|item2;
  52. c->regs[15]+=2;
  53. status = true;
  54. break;
  55. case I_CLD:
  56. c->state &= 0xFFFD;
  57. status = true;
  58. break;
  59. case I_STD:
  60. c->state |= 0x0002;
  61. status = true;
  62. break;
  63. }
  64. break;
  65.  
  66. case 0x01: // OPS I OPNUM Operations with one register operand
  67. switch((XIS_X_REG&OP1)>>5){
  68. case(0x00):
  69. D=OP2>>2;
  70. switch(OP1){
  71. case I_NEG:
  72. c->regs[D] = -1 * c->regs[D];
  73. status = true;
  74. break;
  75. case I_NOT:
  76. if (c->regs[D] == 0){
  77. c->regs[D] = 1;
  78. }
  79. else{
  80. c->regs[D] = 0;
  81. }
  82. status = true;
  83. break;
  84. case I_PUSH:
  85. c->regs[15]-=2;
  86. c->memory[c->regs[15]] = (c->regs[D]&0xFF00)>>8;
  87. c->memory[c->regs[15+1]] = c->regs[D]&0x00FF;
  88. status = true;
  89. break;
  90. case I_POP:
  91. c->regs[D] = c->memory[c->regs[15]];
  92. c->regs[15]+=2;
  93. status = true;
  94. break;
  95. case I_JMPR:
  96. c->pc = c->regs[D];
  97. status = true;
  98. break;
  99. case I_CALLR:
  100. c->regs[15]-=2;
  101. c->memory[c->regs[15]] = c->pc;
  102. c->pc = c->regs[D];
  103. status = true;
  104. break;
  105. case I_OUT:
  106. item1 = c->regs[D];
  107. printf("%c \n", item1);
  108. case I_INC:
  109. c->regs[D]++;
  110. status = true;
  111. break;
  112. case I_DEC:
  113. c->regs[D]--;
  114. status = true;
  115. break;
  116. }
  117. break;
  118.  
  119. case(0x01):
  120. L=OP2;
  121. switch(OP1){
  122. case I_BR:
  123. if((c->state&0x0001) == 0x0001){
  124. c->pc = c->pc + (short)L;
  125. }
  126. status = true;
  127. break;
  128. case I_JR:
  129. c->pc = c->pc + (short)L;
  130. status = true;
  131. break;
  132. }
  133. break;
  134. }
  135. break;
  136.  
  137. case 0x02: // OPS OPNUM Operations with two register operands
  138. S = (OP2>>8);
  139. D = (OP2&0x00Ff);
  140. switch(OP1){
  141. case I_ADD:
  142. c->regs[D] = c->regs[D] + c->regs[S];
  143. status = true;
  144. break;
  145. case I_SUB:
  146. c->regs[D] = c->regs[D] - c->regs[S];
  147. status = true;
  148. break;
  149. case I_MUL:
  150. c->regs[D] = c->regs[D] * c->regs[S];
  151. status = true;
  152. break;
  153. case I_DIV:
  154. c->regs[D] = c->regs[D] / c->regs[S];
  155. status = true;
  156. break;
  157. case I_AND:
  158. c->regs[D] = c->regs[D] & c->regs[S];
  159. status = true;
  160. break;
  161. case I_OR:
  162. c->regs[D] = c->regs[D] | c->regs[S];
  163. status = true;
  164. break;
  165. case I_XOR:
  166. c->regs[D] = c->regs[D] ^ c->regs[S];
  167. status = true;
  168. break;
  169. case I_SHR:
  170. c->regs[D] = c->regs[D] >> c->regs[S];
  171. status = true;
  172. break;
  173. case I_SHL:
  174. c->regs[D] = c->regs[D] << c->regs[S];
  175. status = true;
  176. break;
  177. case I_TEST:
  178. if((c->regs[S]&c->regs[D])!=0){
  179. c->state |= 0x0002;
  180. }
  181. else{
  182. c->state &= 0xFFFE;
  183. }
  184. status = true;
  185. break;
  186. case I_CMP:
  187. if((c->regs[S] < c->regs[D])!=0){
  188. c->state |= 0x0001;
  189. }
  190. else{
  191. c->state &= 0xFFFE;
  192. }
  193. status = true;
  194. break;
  195. case I_EQU:
  196. if((c->regs[S] == c->regs[D])!=0){
  197. c->state |= 0x0001;
  198. }
  199. else{
  200. c->state &= 0xFFFE;
  201. }
  202. status = true;
  203. break;
  204. case I_MOV:
  205. c->regs[D] = c->regs[S];
  206. status = true;
  207. break;
  208. case I_LOAD:
  209. c->regs[D] = c->memory[c->regs[S]];
  210. status = true;
  211. break;
  212. case I_STOR:
  213. c->regs[S] = c->memory[c->regs[D]];
  214. status = true;
  215. break;
  216. case I_LOADB:
  217. status = true;
  218. break;
  219. case I_STORB:
  220. status = true;
  221. break;
  222. }
  223. break;
  224.  
  225. case 0x03:
  226. switch((XIS_EXTENDED&OP1)>>5){
  227. case(0x00): /* OPS R OPNUM X Operations with one immediate operand */
  228. L = (c->memory[c->pc]<<8)|c->memory[c->pc+1];//this is assuming that you already did pc+=2 at the start
  229. switch(OP1){
  230. case I_JMP:
  231. c->pc = c->memory[c->regs[L]];
  232. status = true;
  233. break;
  234. case I_CALL:
  235. c->regs[15]-=1;
  236. c->memory[c->regs[15]] = c->pc&0x00FF;
  237. c->regs[15]-=1;
  238. c->memory[c->regs[15]] = (c->pc&0xFF00>>8);
  239. c->pc = c->memory[c->regs[L]];
  240. status = true;
  241. break;
  242. }
  243. break;
  244. case(0x01): /* OPS R OPNUM X Ops with 1 imm. and 1 reg. operand */
  245. D = (OP2>>8);
  246. a = (c->memory[c->pc]<<8)|(c->memory[c->pc+1]);
  247. switch(OP1){
  248. case I_LOADI:
  249. c->regs[D] = a;
  250. c->pc = c->pc+2;
  251. status = true;
  252. break;
  253. }
  254. break;
  255. }
  256. break;
  257. }
  258. return status; //Returns True (1) if succesfull or False (0) for failed
  259. }
  260.  
  261. /* Not needed for assignment 1 */
  262. int xcpu_exception( xcpu *c, unsigned int ex ) {
  263. return 0;
  264. }
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement
Public Pastes
Advertisement
We use cookies for various purposes including analytics. By continuing to use Pastebin, you agree to our use of cookies as described in the Cookies Policy.  OK, I Understand
Not a member of Pastebin yet?
Sign Up, it unlocks many cool features!