Auto VHDL testbench generator

#!/usr/bin/perl
# Author: Chris Cross
# URL: http://www.beesnotincluded.com
# License: GPLv2
# Status: Underdevelopment


use feature ':5.10';
say "Auto VHDL Test bench generator 1.0";


#Process command line arguments
if(int(@ARGV) >= 1){
    $infile = $ARGV[0];   #First argument is input vhdl file

   if(int(@ARGV) >= 2) {    #Second argument is output vhdl file
        $outfile = $ARGV[1];
    } else {
        $outfile = $ARGV[0];
        $outfile =~ s/\.vhdl*$/_tb.vhd/;
    }
} else {
    say "Usage: $0 infile.vhd [outfile.vhd]";
    exit -1;
}
say "Generating testbench for file:\t", $infile;
say "Writing testbench to file:\t", $outfile;

open my $vhdlfile, $infile or say "Can't open $infile" and exit -1;

my @pnames = ();        #stores port names
my @ptypes = ();        #stores port types (std_logic, std_logic_vector)
my @pdirs = ();         #stores
my @pcomments = ();     #sotres eol comments associated with ports
my $entity = "";        #stores entity name
my $architecture = "";  #stores architecture name
my @includes = ();      #stores any library includes


my $line;               #
while ($line = <$vhdlfile>){

    #Search for ports
    if($line =~ /(\w+)\s*:\s*(INOUT|IN|OUT)\s*([^;-]+)\s*[;-]\s*-*\s*(.*)/i) {
        #store the signal name in the appropriate array
        push(@pnames, $1);
        push(@pcomments, $4);

        #Strip trailing whitespace
        my $type = $3;
        $type =~s/\s+$//;
        push(@ptypes, $type);

        #Deduce the port type
        if($2 =~ /IN/i) {
            push(@pdir, "IN");
        }
        elsif($2 =~ /OUT/i) {
            push(@pdir, "OUT");
        }
        elsif($2 =~ /INOUT/i) {
            push(@pdir, "INOUT");
        }
    # Search for entity name
    } elsif($line =~ /entity\s*(\w+)\s*is/i) {
        $entity = $1;
    # Search for architecture type
    } elsif($line =~ /architecture\s*(\w+)\s*of/i) {
        $architecture = $1;
    # Search for library or use statements
    } elsif($line =~ /^(use|library).*/i) {
        $line =~s/\s*$//;
        push(@includes, $line);
    }
}

#Open the output file
open $tbfile, '>', $outfile or say "Can't open $outfile" and exit -1;

#Write header text
print $tbfile "--\t**************************************************************\n";
print $tbfile "--\tAuto-generated testbench for design entity: $entity\n";
print $tbfile "--\tGenerated on: ".localtime() , "\n";
print $tbfile "--\t**************************************************************\n\n";

#Write library imports necessary for tesbench
print $tbfile "-- Library includes\n";
foreach my $stmt (@includes){
    print $tbfile $stmt, "\n";
}
print $tbfile "\n";

#Create useful variables
$entity_tb = $entity . "_tb";


#Write entity declaration for testbench
print $tbfile "-- Entity declaration\n";
print $tbfile "entity $entity_tb is\n";
print $tbfile "end entity $entity_tb;\n\n";

#Write architecture for test bench
print $tbfile "-- Architecture definition\n";
print $tbfile "architecture sim of $entity_tb is\n";

#Write the signal declarations
print $tbfile "-- Signal declarations\n";
for (my $i = 0; $i < int(@pnames); $i++) {
    print $tbfile "\tsignal ", $pnames[$i], "\t: ", $ptypes[$i], "; --", $pcomments[$i], "\n";
}

#print placeholder for testbench signal declarations
print $tbfile "-- Testbench signal declarations\n\n";

print $tbfile "begin\n";

#Instantiate the component
print $tbfile "-- Component declarations\n";
print $tbfile 'dut : entity work.',$entity,'(',$architecture,') port map(', "\n";
for (my $i = 0; $i < int(@pnames); $i++) {
    my $ending = ",\n";
    if($i == @pnames-1) {
        $ending = "\n";
    }
    print $tbfile "\t", $pnames[$i], "\t=>", $pnames[$i], $ending;
}
print $tbfile ");\n";

#End architecture
print $tbfile "end architecture sim;";