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  1. /* ###################################################################
  2. **     THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
  3. **     Filename    : Cpu.c
  4. **     Project     : ProcessorExpert
  5. **     Processor   : MK60DN512VLQ10
  6. **     Component   : MK60DN512LQ10
  7. **     Version     : Component 01.000, Driver 01.04, CPU db: 3.00.000
  8. **     Datasheet   : K60P144M100SF2V2RM Rev. 2, Jun 2012
  9. **     Compiler    : GNU C Compiler
  10. **     Date/Time   : 2013-06-24, 21:00, # CodeGen: 84
  11. **     Abstract    :
  12. **
  13. **     Settings    :
  14. **
  15. **     Contents    :
  16. **         No public methods
  17. **
  18. **     Copyright : 1997 - 2013 Freescale Semiconductor, Inc. All Rights Reserved.
  19. **     SOURCE DISTRIBUTION PERMISSIBLE as directed in End User License Agreement.
  20. **    
  21. **     http      : www.freescale.com
  22. **     mail      : support@freescale.com
  23. ** ###################################################################*/
  24. /*!
  25. ** @file Cpu.c
  26. ** @version 01.04
  27. ** @brief
  28. **
  29. */        
  30. /*!
  31. **  @addtogroup Cpu_module Cpu module documentation
  32. **  @{
  33. */        
  34.  
  35. /* MODULE Cpu. */
  36.  
  37. /* {Default RTOS Adapter} No RTOS includes */
  38. #include "AS1.h"
  39. #include "PE_Types.h"
  40. #include "PE_Error.h"
  41. #include "PE_Const.h"
  42. #include "IO_Map.h"
  43. #include "Events.h"
  44. #include "Cpu.h"
  45.  
  46. #ifdef __cplusplus
  47. extern "C" {
  48. #endif
  49.  
  50. /* Global variables */
  51. volatile uint8_t SR_reg;               /* Current value of the FAULTMASK register */
  52. volatile uint8_t SR_lock = 0x00U;      /* Lock */
  53.  
  54. /*
  55. ** ===================================================================
  56. **     Method      :  Cpu_SetBASEPRI (component MK60DN512LQ10)
  57. **
  58. **     Description :
  59. **         This method sets the BASEPRI core register.
  60. **         This method is internal. It is used by Processor Expert only.
  61. ** ===================================================================
  62. */
  63. void Cpu_SetBASEPRI(uint32_t Level);
  64.  
  65. /*
  66. ** ===================================================================
  67. **     Method      :  Cpu_INT_NMIInterrupt (component MK60DN512LQ10)
  68. **
  69. **     Description :
  70. **         This ISR services the Non Maskable Interrupt interrupt.
  71. **         This method is internal. It is used by Processor Expert only.
  72. ** ===================================================================
  73. */
  74. PE_ISR(Cpu_INT_NMIInterrupt)
  75. {
  76.   Cpu_OnNMIINT0();
  77. }
  78.  
  79. /*
  80. ** ===================================================================
  81. **     Method      :  Cpu_Cpu_Interrupt (component MK60DN512LQ10)
  82. **
  83. **     Description :
  84. **         This ISR services an unused interrupt/exception vector.
  85. **         This method is internal. It is used by Processor Expert only.
  86. ** ===================================================================
  87. */
  88. PE_ISR(Cpu_Interrupt)
  89. {
  90.   /* This code can be changed using the CPU component property "Build Options / Unhandled int code" */
  91.   PE_DEBUGHALT();
  92. }
  93.  
  94.  
  95. /*** !!! Here you can place your own code using property "User data declarations" on the build options tab. !!! ***/
  96.  
  97. /*lint -esym(765,__init_hardware) Disable MISRA rule (8.10) checking for symbols (__init_hardware). The function is linked to the EWL library */
  98. /*lint -esym(765,Cpu_Interrupt) Disable MISRA rule (8.10) checking for symbols (Cpu_Interrupt). */
  99. void __init_hardware(void)
  100. {
  101.  
  102.   /*** !!! Here you can place your own code before PE initialization using property "User code before PE initialization" on the build options tab. !!! ***/
  103.  
  104.   /*** ### MK60DN512VLQ10 "Cpu" init code ... ***/
  105.   /*** PE initialization code after reset ***/
  106.   SCB_VTOR = (uint32_t)(&__vect_table); /* Set the interrupt vector table position */
  107.   /* Disable the WDOG module */
  108.   /* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */
  109.   WDOG_UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
  110.   /* WDOG_UNLOCK: WDOGUNLOCK=0xD928 */
  111.   WDOG_UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
  112.   /* WDOG_STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,??=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
  113.   WDOG_STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
  114.                  WDOG_STCTRLH_WAITEN_MASK |
  115.                  WDOG_STCTRLH_STOPEN_MASK |
  116.                  WDOG_STCTRLH_ALLOWUPDATE_MASK |
  117.                  WDOG_STCTRLH_CLKSRC_MASK |
  118.                  0x0100U;      
  119.   /* System clock initialization */
  120.   /* SIM_SCGC5: PORTE=1,PORTA=1 */
  121.   SIM_SCGC5 |= (SIM_SCGC5_PORTE_MASK | SIM_SCGC5_PORTA_MASK); /* Enable clock gate for ports to enable pin routing */
  122.   /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=3,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
  123.   SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
  124.                 SIM_CLKDIV1_OUTDIV2(0x01) |
  125.                 SIM_CLKDIV1_OUTDIV3(0x01) |
  126.                 SIM_CLKDIV1_OUTDIV4(0x03); /* Update system prescalers */
  127.   /* SIM_SOPT2: PLLFLLSEL=1 */
  128.   SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; /* Select PLL as a clock source for various peripherals */
  129.   /* SIM_SOPT1: OSC32KSEL=3 */
  130.   SIM_SOPT1 |= SIM_SOPT1_OSC32KSEL(0x03); /* LPO 1kHz oscillator drives 32 kHz clock for various peripherals */
  131.   /* PORTA_PCR18: ISF=0,MUX=0 */
  132.   PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));                                  
  133.   /* Switch to FBE Mode */
  134.   /* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
  135.   MCG_C2 = MCG_C2_RANGE0(0x02);                                  
  136.   /* OSC_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
  137.   OSC_CR = OSC_CR_ERCLKEN_MASK;                                  
  138.   /* MCG_C7: OSCSEL=0 */
  139.   MCG_C7 &= (uint8_t)~(uint8_t)(MCG_C7_OSCSEL_MASK);                                  
  140.   /* MCG_C1: CLKS=2,FRDIV=5,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
  141.   MCG_C1 = (MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x05) | MCG_C1_IRCLKEN_MASK);                                  
  142.   /* MCG_C4: DMX32=0,DRST_DRS=0 */
  143.   MCG_C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));                                  
  144.   /* MCG_C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x0F */
  145.   MCG_C5 = MCG_C5_PRDIV0(0x0F);                                  
  146.   /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=8 */
  147.   MCG_C6 = MCG_C6_VDIV0(0x08);                                  
  148.   while((MCG_S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
  149.   }
  150.   while((MCG_S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
  151.   }
  152.   /* Switch to PBE Mode */
  153.   /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=8 */
  154.   MCG_C6 = (MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0x08));                                  
  155.   while((MCG_S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
  156.   }
  157.   while((MCG_S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */
  158.   }
  159.   /* Switch to PEE Mode */
  160.   /* MCG_C1: CLKS=0,FRDIV=5,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
  161.   MCG_C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x05) | MCG_C1_IRCLKEN_MASK);                                  
  162.   while((MCG_S & 0x0CU) != 0x0CU) {    /* Wait until output of the PLL is selected */
  163.   }
  164.   /*** End of PE initialization code after reset ***/
  165.  
  166.   /*** !!! Here you can place your own code after PE initialization using property "User code after PE initialization" on the build options tab. !!! ***/
  167.  
  168. }
  169.  
  170. /*
  171. ** ===================================================================
  172. **     Method      :  Cpu_SetBASEPRI (component MK60DN512LQ10)
  173. **
  174. **     Description :
  175. **         This method sets the BASEPRI core register.
  176. **         This method is internal. It is used by Processor Expert only.
  177. ** ===================================================================
  178. */
  179. /*lint -save  -e586 -e950 Disable MISRA rule (2.1,1.1) checking. */
  180. #ifdef _lint
  181.   #define Cpu_SetBASEPRI(Level)  /* empty */
  182. #else
  183. void Cpu_SetBASEPRI(uint32_t Level) {
  184.   asm ("msr basepri, %[input]"::[input] "r" (Level):);
  185. }
  186. #endif
  187. /*lint -restore Enable MISRA rule (2.1,1.1) checking. */
  188.  
  189.  
  190. /*
  191. ** ===================================================================
  192. **     Method      :  PE_low_level_init (component MK60DN512LQ10)
  193. **
  194. **     Description :
  195. **         Initializes beans and provides common register initialization.
  196. **         The method is called automatically as a part of the
  197. **         application initialization code.
  198. **         This method is internal. It is used by Processor Expert only.
  199. ** ===================================================================
  200. */
  201. void PE_low_level_init(void)
  202. {
  203.   #ifdef PEX_RTOS_INIT
  204.     PEX_RTOS_INIT();                   /* Initialization of the selected RTOS. Macro is defined by the RTOS component. */
  205.   #endif
  206.       /* Initialization of the SIM module */
  207.   /* PORTA_PCR4: ISF=0,MUX=7 */
  208.   PORTA_PCR4 = (uint32_t)((PORTA_PCR4 & (uint32_t)~(uint32_t)(
  209.                 PORT_PCR_ISF_MASK
  210.                )) | (uint32_t)(
  211.                 PORT_PCR_MUX(0x07)
  212.                ));                                  
  213.         /* Initialization of the RCM module */
  214.   /* RCM_RPFW: RSTFLTSEL=0 */
  215.   RCM_RPFW &= (uint8_t)~(uint8_t)(RCM_RPFW_RSTFLTSEL(0x1F));                                  
  216.   /* RCM_RPFC: RSTFLTSS=0,RSTFLTSRW=0 */
  217.   RCM_RPFC &= (uint8_t)~(uint8_t)(
  218.                RCM_RPFC_RSTFLTSS_MASK |
  219.                RCM_RPFC_RSTFLTSRW(0x03)
  220.               );                                  
  221.         /* Initialization of the FTFL_FlashConfig module */
  222.   /* SIM_SCGC7: MPU=1 */
  223.   SIM_SCGC7 |= SIM_SCGC7_MPU_MASK;                                  
  224.         /* Initialization of the MPU module */
  225.   /* MPU_CESR: SPERR=0,VLD=0 */
  226.   MPU_CESR &= (uint32_t)~(uint32_t)((MPU_CESR_SPERR(0x1F) | MPU_CESR_VLD_MASK));                                  
  227.       /* Initialization of the PMC module */
  228.   /* PMC_LVDSC1: LVDACK=1,LVDIE=0,LVDRE=1,LVDV=0 */
  229.   PMC_LVDSC1 = (uint8_t)((PMC_LVDSC1 & (uint8_t)~(uint8_t)(
  230.                 PMC_LVDSC1_LVDIE_MASK |
  231.                 PMC_LVDSC1_LVDV(0x03)
  232.                )) | (uint8_t)(
  233.                 PMC_LVDSC1_LVDACK_MASK |
  234.                 PMC_LVDSC1_LVDRE_MASK
  235.                ));                                  
  236.   /* PMC_LVDSC2: LVWACK=1,LVWIE=0,LVWV=0 */
  237.   PMC_LVDSC2 = (uint8_t)((PMC_LVDSC2 & (uint8_t)~(uint8_t)(
  238.                 PMC_LVDSC2_LVWIE_MASK |
  239.                 PMC_LVDSC2_LVWV(0x03)
  240.                )) | (uint8_t)(
  241.                 PMC_LVDSC2_LVWACK_MASK
  242.                ));                                  
  243.   /* PMC_REGSC: BGEN=0,ACKISO=0,BGBE=0 */
  244.   PMC_REGSC &= (uint8_t)~(uint8_t)(
  245.                 PMC_REGSC_BGEN_MASK |
  246.                 PMC_REGSC_ACKISO_MASK |
  247.                 PMC_REGSC_BGBE_MASK
  248.                );                                  
  249.   /* SMC_PMPROT: ??=0,??=0,AVLP=0,??=0,ALLS=0,??=0,AVLLS=0,??=0 */
  250.   SMC_PMPROT = 0x00U;                  /* Setup Power mode protection register */
  251.   /* Common initialization of the CPU registers */
  252.   /* NVICIP20: PRI20=0 */
  253.   NVICIP20 = NVIC_IP_PRI20(0x00);                                  
  254.   /* ### Serial_LDD "AS1" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */
  255.   (void)AS1_Init(NULL);
  256.   /* Enable interrupts of the given priority level */
  257.   Cpu_SetBASEPRI(16U);
  258. }
  259.   /* Flash configuration field */
  260.   __attribute__ ((section (".cfmconfig"))) const uint8_t _cfm[0x10] = {
  261.    /* NV_BACKKEY3: KEY=0xFF */
  262.     0xFFU,
  263.    /* NV_BACKKEY2: KEY=0xFF */
  264.     0xFFU,
  265.    /* NV_BACKKEY1: KEY=0xFF */
  266.     0xFFU,
  267.    /* NV_BACKKEY0: KEY=0xFF */
  268.     0xFFU,
  269.    /* NV_BACKKEY7: KEY=0xFF */
  270.     0xFFU,
  271.    /* NV_BACKKEY6: KEY=0xFF */
  272.     0xFFU,
  273.    /* NV_BACKKEY5: KEY=0xFF */
  274.     0xFFU,
  275.    /* NV_BACKKEY4: KEY=0xFF */
  276.     0xFFU,
  277.    /* NV_FPROT3: PROT=0xFF */
  278.     0xFFU,
  279.    /* NV_FPROT2: PROT=0xFF */
  280.     0xFFU,
  281.    /* NV_FPROT1: PROT=0xFF */
  282.     0xFFU,
  283.    /* NV_FPROT0: PROT=0xFF */
  284.     0xFFU,
  285.    /* NV_FSEC: KEYEN=1,MEEN=3,FSLACC=3,SEC=2 */
  286.     0x7EU,
  287.    /* NV_FOPT: ??=1,??=1,??=1,??=1,??=1,??=1,EZPORT_DIS=1,LPBOOT=1 */
  288.     0xFFU,
  289.    /* NV_FEPROT: EPROT=0xFF */
  290.     0xFFU,
  291.    /* NV_FDPROT: DPROT=0xFF */
  292.     0xFFU
  293.   };
  294.  
  295. /* END Cpu. */
  296.  
  297. #ifdef __cplusplus
  298. }  /* extern "C" */
  299. #endif
  300.  
  301. /*!
  302. ** @}
  303. */
  304. /*
  305. ** ###################################################################
  306. **
  307. **     This file was created by Processor Expert 10.2 [05.06]
  308. **     for the Freescale Kinetis series of microcontrollers.
  309. **
  310. ** ###################################################################
  311. */
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